19fd9f1d0Sshengfei Xu# 2*5be66449SBoyan Karatotev# Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved. 39fd9f1d0Sshengfei Xu# 49fd9f1d0Sshengfei Xu# SPDX-License-Identifier: BSD-3-Clause 59fd9f1d0Sshengfei Xu# 69fd9f1d0Sshengfei Xu 79fd9f1d0Sshengfei XuRK_PLAT := plat/rockchip 89fd9f1d0Sshengfei XuRK_PLAT_SOC := ${RK_PLAT}/${PLAT} 99fd9f1d0Sshengfei XuRK_PLAT_COMMON := ${RK_PLAT}/common 109fd9f1d0Sshengfei Xu 119fd9f1d0Sshengfei XuDISABLE_BIN_GENERATION := 1 129fd9f1d0Sshengfei XuGICV3_SUPPORT_GIC600 := 1 139fd9f1d0Sshengfei Xuinclude lib/coreboot/coreboot.mk 149fd9f1d0Sshengfei Xuinclude lib/libfdt/libfdt.mk 159fd9f1d0Sshengfei Xuinclude lib/xlat_tables_v2/xlat_tables.mk 169fd9f1d0Sshengfei Xu# GIC-600 configuration 179fd9f1d0Sshengfei XuGICV3_IMPL := GIC600 189fd9f1d0Sshengfei Xu# Include GICv3 driver files 199fd9f1d0Sshengfei Xuinclude drivers/arm/gic/v3/gicv3.mk 209fd9f1d0Sshengfei Xu 219fd9f1d0Sshengfei XuPLAT_INCLUDES := -Iinclude/bl31 \ 229fd9f1d0Sshengfei Xu -Iinclude/common \ 239fd9f1d0Sshengfei Xu -Iinclude/drivers \ 249fd9f1d0Sshengfei Xu -Iinclude/drivers/arm \ 259fd9f1d0Sshengfei Xu -Iinclude/drivers/auth \ 269fd9f1d0Sshengfei Xu -Iinclude/drivers/io \ 279fd9f1d0Sshengfei Xu -Iinclude/drivers/ti/uart \ 289fd9f1d0Sshengfei Xu -Iinclude/lib \ 299fd9f1d0Sshengfei Xu -Iinclude/lib/cpus/${ARCH} \ 309fd9f1d0Sshengfei Xu -Iinclude/lib/el3_runtime \ 319fd9f1d0Sshengfei Xu -Iinclude/lib/pmf \ 329fd9f1d0Sshengfei Xu -Iinclude/lib/psci \ 339fd9f1d0Sshengfei Xu -Iinclude/plat/common \ 349fd9f1d0Sshengfei Xu -Iinclude/services \ 359fd9f1d0Sshengfei Xu -Iinclude/plat/common/ \ 369fd9f1d0Sshengfei Xu -Idrivers/arm/gic/v3/ \ 379fd9f1d0Sshengfei Xu -I${RK_PLAT_COMMON}/ \ 389fd9f1d0Sshengfei Xu -I${RK_PLAT_COMMON}/pmusram/ \ 399fd9f1d0Sshengfei Xu -I${RK_PLAT_COMMON}/include/ \ 409fd9f1d0Sshengfei Xu -I${RK_PLAT_COMMON}/drivers/pmu/ \ 419fd9f1d0Sshengfei Xu -I${RK_PLAT_COMMON}/drivers/parameter/ \ 429fd9f1d0Sshengfei Xu -I${RK_PLAT_SOC}/ \ 439fd9f1d0Sshengfei Xu -I${RK_PLAT_SOC}/drivers/pmu/ \ 449fd9f1d0Sshengfei Xu -I${RK_PLAT_SOC}/drivers/soc/ \ 459fd9f1d0Sshengfei Xu -I${RK_PLAT_SOC}/include/ 469fd9f1d0Sshengfei Xu 479fd9f1d0Sshengfei XuRK_GIC_SOURCES := ${GICV3_SOURCES} \ 489fd9f1d0Sshengfei Xu plat/common/plat_gicv3.c \ 499fd9f1d0Sshengfei Xu ${RK_PLAT}/common/rockchip_gicv3.c 509fd9f1d0Sshengfei Xu 519fd9f1d0Sshengfei XuPLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \ 529fd9f1d0Sshengfei Xu common/desc_image_load.c \ 539fd9f1d0Sshengfei Xu plat/common/aarch64/crash_console_helpers.S \ 549fd9f1d0Sshengfei Xu lib/bl_aux_params/bl_aux_params.c \ 559fd9f1d0Sshengfei Xu plat/common/plat_psci_common.c 569fd9f1d0Sshengfei Xu 579fd9f1d0Sshengfei Xuifneq (${ENABLE_STACK_PROTECTOR},0) 589fd9f1d0Sshengfei XuPLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c 599fd9f1d0Sshengfei Xuendif 609fd9f1d0Sshengfei Xu 619fd9f1d0Sshengfei XuBL31_SOURCES += ${RK_GIC_SOURCES} \ 629fd9f1d0Sshengfei Xu drivers/arm/cci/cci.c \ 639fd9f1d0Sshengfei Xu lib/cpus/aarch64/cortex_a55.S \ 649fd9f1d0Sshengfei Xu drivers/ti/uart/aarch64/16550_console.S \ 659fd9f1d0Sshengfei Xu drivers/delay_timer/delay_timer.c \ 669fd9f1d0Sshengfei Xu drivers/delay_timer/generic_delay_timer.c \ 679fd9f1d0Sshengfei Xu $(LIBFDT_SRCS) \ 689fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ 699fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/bl31_plat_setup.c \ 709fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/params_setup.c \ 719fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/plat_pm.c \ 729fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/plat_topology.c \ 739fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ 749fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \ 759fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ 769fd9f1d0Sshengfei Xu ${RK_PLAT_COMMON}/aarch64/platform_common.c \ 779fd9f1d0Sshengfei Xu ${RK_PLAT_SOC}/drivers/soc/soc.c \ 789fd9f1d0Sshengfei Xu ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ 799fd9f1d0Sshengfei Xu ${RK_PLAT_SOC}/plat_sip_calls.c 809fd9f1d0Sshengfei Xu 819fd9f1d0Sshengfei XuENABLE_PLAT_COMPAT := 0 829fd9f1d0Sshengfei XuMULTI_CONSOLE_API := 1 839fd9f1d0Sshengfei Xu# System coherency is managed in hardware 849fd9f1d0Sshengfei XuHW_ASSISTED_COHERENCY := 1 859fd9f1d0Sshengfei Xu#Enable errata for cortex_a55 869fd9f1d0Sshengfei XuERRATA_A55_1530923 := 1 879fd9f1d0Sshengfei Xu 889fd9f1d0Sshengfei Xu# When building for systems with hardware-assisted coherency, there's no need to 899fd9f1d0Sshengfei Xu# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 909fd9f1d0Sshengfei XuUSE_COHERENT_MEM := 0 919fd9f1d0Sshengfei Xu 929fd9f1d0Sshengfei Xu$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER)) 93*5be66449SBoyan KaratotevPLAT_EXTRA_LD_SCRIPT := 1 949fd9f1d0Sshengfei Xu 959fd9f1d0Sshengfei Xu# Do not enable SVE 969fd9f1d0Sshengfei XuENABLE_SVE_FOR_NS := 0 97