1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <rk3568_def.h> 13 14 #define DEBUG_XLAT_TABLE 0 15 16 /******************************************************************************* 17 * Platform binary types for linking 18 ******************************************************************************/ 19 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20 #define PLATFORM_LINKER_ARCH aarch64 21 22 /******************************************************************************* 23 * Generic platform constants 24 ******************************************************************************/ 25 26 /* Size of cacheable stacks */ 27 #if DEBUG_XLAT_TABLE 28 #define PLATFORM_STACK_SIZE 0x800 29 #elif IMAGE_BL1 30 #define PLATFORM_STACK_SIZE 0x440 31 #elif IMAGE_BL2 32 #define PLATFORM_STACK_SIZE 0x400 33 #elif IMAGE_BL31 34 #define PLATFORM_STACK_SIZE 0x800 35 #elif IMAGE_BL32 36 #define PLATFORM_STACK_SIZE 0x440 37 #endif 38 39 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 40 41 #define PLATFORM_SYSTEM_COUNT 1 42 #define PLATFORM_CLUSTER_COUNT 1 43 #define PLATFORM_CLUSTER0_CORE_COUNT 4 44 45 #define PLATFORM_CLUSTER1_CORE_COUNT 0 46 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47 PLATFORM_CLUSTER0_CORE_COUNT) 48 49 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50 PLATFORM_CLUSTER_COUNT + \ 51 PLATFORM_CORE_COUNT) 52 53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 54 55 #define PLAT_RK_CLST_TO_CPUID_SHIFT 8 56 57 /* 58 * This macro defines the deepest retention state possible. A higher state 59 * id will represent an invalid or a power down state. 60 */ 61 #define PLAT_MAX_RET_STATE 1 62 63 /* 64 * This macro defines the deepest power down states possible. Any state ID 65 * higher than this is invalid. 66 */ 67 #define PLAT_MAX_OFF_STATE 2 68 /******************************************************************************* 69 * Platform memory map related constants 70 ******************************************************************************/ 71 /* TF txet, ro, rw, Size: 512KB */ 72 #define TZRAM_BASE (0x0) 73 #define TZRAM_SIZE (0x100000) 74 75 /******************************************************************************* 76 * BL31 specific defines. 77 ******************************************************************************/ 78 /* 79 * Put BL3-1 at the top of the Trusted RAM 80 */ 81 #define BL31_BASE (TZRAM_BASE + 0x40000) 82 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 83 84 /******************************************************************************* 85 * Platform specific page table and MMU setup constants 86 ******************************************************************************/ 87 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 88 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 89 90 #define ADDR_SPACE_SIZE (1ull << 32) 91 #define MAX_XLAT_TABLES 18 92 #define MAX_MMAP_REGIONS 27 93 94 /******************************************************************************* 95 * Declarations and constants to access the mailboxes safely. Each mailbox is 96 * aligned on the biggest cache line size in the platform. This is known only 97 * to the platform as it might have a combination of integrated and external 98 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 99 * line at any cache level. They could belong to different cpus/clusters & 100 * get written while being protected by different locks causing corruption of 101 * a valid mailbox address. 102 ******************************************************************************/ 103 #define CACHE_WRITEBACK_SHIFT 6 104 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 105 106 /* 107 * Define GICD and GICC and GICR base 108 */ 109 #define PLAT_RK_GICD_BASE PLAT_GICD_BASE 110 #define PLAT_RK_GICC_BASE PLAT_GICC_BASE 111 #define PLAT_RK_GICR_BASE PLAT_GICR_BASE 112 113 /* 114 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 115 * terminology. On a GICv2 system or mode, the lists will be merged and treated 116 * as Group 0 interrupts. 117 */ 118 119 #define PLAT_RK_GICV3_G1S_IRQS \ 120 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 121 INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 122 123 #define PLAT_RK_GICV3_G0_IRQS \ 124 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 125 INTR_GROUP0, GIC_INTR_CFG_LEVEL) 126 127 #define PLAT_RK_UART_BASE FPGA_UART_BASE 128 #define PLAT_RK_UART_CLOCK FPGA_UART_CLOCK 129 #define PLAT_RK_UART_BAUDRATE FPGA_BAUDRATE 130 131 #define PLAT_RK_PRIMARY_CPU 0x0 132 133 #define ATAGS_PHYS_SIZE 0x2000 134 #define ATAGS_PHYS_BASE (0x200000 - ATAGS_PHYS_SIZE)/* [2M-8K, 2M] */ 135 136 #endif /* __PLATFORM_DEF_H__ */ 137