1*9fd9f1d0Sshengfei Xu/* 2*9fd9f1d0Sshengfei Xu * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3*9fd9f1d0Sshengfei Xu * 4*9fd9f1d0Sshengfei Xu * SPDX-License-Identifier: BSD-3-Clause 5*9fd9f1d0Sshengfei Xu */ 6*9fd9f1d0Sshengfei Xu#ifndef ROCKCHIP_PLAT_LD_S 7*9fd9f1d0Sshengfei Xu#define ROCKCHIP_PLAT_LD_S 8*9fd9f1d0Sshengfei Xu 9*9fd9f1d0Sshengfei XuMEMORY { 10*9fd9f1d0Sshengfei Xu PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 11*9fd9f1d0Sshengfei Xu} 12*9fd9f1d0Sshengfei Xu 13*9fd9f1d0Sshengfei XuSECTIONS 14*9fd9f1d0Sshengfei Xu{ 15*9fd9f1d0Sshengfei Xu . = PMUSRAM_BASE; 16*9fd9f1d0Sshengfei Xu 17*9fd9f1d0Sshengfei Xu /* 18*9fd9f1d0Sshengfei Xu * pmu_cpuson_entrypoint request address 19*9fd9f1d0Sshengfei Xu * align 64K when resume, so put it in the 20*9fd9f1d0Sshengfei Xu * start of pmusram 21*9fd9f1d0Sshengfei Xu */ 22*9fd9f1d0Sshengfei Xu .pmusram : { 23*9fd9f1d0Sshengfei Xu ASSERT(. == ALIGN(64 * 1024), 24*9fd9f1d0Sshengfei Xu ".pmusram.entry request 64K aligned."); 25*9fd9f1d0Sshengfei Xu KEEP(*(.pmusram.entry)) 26*9fd9f1d0Sshengfei Xu 27*9fd9f1d0Sshengfei Xu __bl31_pmusram_text_start = .; 28*9fd9f1d0Sshengfei Xu *(.pmusram.text) 29*9fd9f1d0Sshengfei Xu *(.pmusram.rodata) 30*9fd9f1d0Sshengfei Xu __bl31_pmusram_text_end = .; 31*9fd9f1d0Sshengfei Xu __bl31_pmusram_data_start = .; 32*9fd9f1d0Sshengfei Xu *(.pmusram.data) 33*9fd9f1d0Sshengfei Xu __bl31_pmusram_data_end = .; 34*9fd9f1d0Sshengfei Xu } >PMUSRAM 35*9fd9f1d0Sshengfei Xu} 36*9fd9f1d0Sshengfei Xu#endif /* ROCKCHIP_PLAT_LD_S */ 37