1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 10 #define RKFPGA_DEV_RNG0_BASE 0xf8000000 11 #define RKFPGA_DEV_RNG0_SIZE 0x07fff000 12 13 #define CRU_MODE_CON00 0x00c0 14 #define PMUCRU_MODE_CON00 0x0080 15 16 #define CRU_GLB_SRST_FST 0x00d4 17 #define GLB_SRST_FST_CFG_VAL 0xfdb9 18 19 #define PMU_GRF_GPIO0A_IOMUX_L 0x00 20 #define PMU_GRF_SOC_CON(i) (0x0100 + i * 4) 21 22 #define CRU_SOFTRST_CON 0x300 23 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) 24 #define CRU_SOFTRSTS_CON_CNT 26 25 #define GRF_DDR_CON3 0x000c 26 #define SGRF_FIREWALL_SLV_CON(i) (0x240 + i * 4) 27 28 #define FIREWALL_DDR_FW_DDR_CON_REG 0x80 29 30 /* low 32 bits */ 31 #define TIMER_LOAD_COUNT0 0x00 32 #define TIMER_LOAD_COUNT1 0x04 33 #define TIMER_CURRENT_VALUE0 0x08 34 #define TIMER_CURRENT_VALUE1 0x0c 35 #define TIMER_CONTROL_REG 0x10 36 #define TIMER_INTSTATUS 0x18 37 #define TIMER_DIS 0x0 38 #define TIMER_EN 0x1 39 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 40 41 #define PMU_GRF_GPIO0B_IOMUX_L 0x0008 42 #define PMUCRU_PMUCLKSEL_CON00 0x0100 43 #define PMUPVTM_BASE 0xfdd80000 44 #define PVTM_CON0 0x0004 45 #define PVTM_CON1 0x0008 46 #define PVTM_STATUS0 0x0080 47 #define PVTM_STATUS1 0x0084 48 #define PMUCRU_PMUGATE_CON01 0x0184 49 #define PVTM_CALC_CNT 0x200 50 #define PMU_GRF_DLL_CON0 0x0180 51 52 enum cru_mode_con00 { 53 CLK_APLL, 54 CLK_DPLL, 55 CLK_CPLL, 56 CLK_GPLL, 57 CLK_REVSERVED, 58 CLK_NPLL, 59 CLK_VPLL, 60 CLK_USBPLL, 61 }; 62 63 #endif /* __SOC_H__ */ 64