1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/xlat_tables/xlat_tables_v2.h> 9 #include <mmio.h> 10 #include <platform_def.h> 11 12 #include <soc.h> 13 14 const mmap_region_t plat_rk_mmap[] = { 15 MAP_REGION_FLAT(RKFPGA_DEV_RNG0_BASE, RKFPGA_DEV_RNG0_SIZE, 16 MT_DEVICE | MT_RW | MT_SECURE), 17 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 18 MT_MEMORY | MT_RW | MT_SECURE), 19 20 { 0 } 21 }; 22 23 /* The RockChip power domain tree descriptor */ 24 const unsigned char rockchip_power_domain_tree_desc[] = { 25 /* No of root nodes */ 26 PLATFORM_SYSTEM_COUNT, 27 /* No of children for the root node */ 28 PLATFORM_CLUSTER_COUNT, 29 /* No of children for the first cluster node */ 30 PLATFORM_CLUSTER0_CORE_COUNT, 31 }; 32 33 static void secure_timer_init(void) 34 { 35 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS); 36 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 37 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 38 39 /* auto reload & enable the timer */ 40 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); 41 } 42 43 static void sgrf_init(void) 44 { 45 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000); 46 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000); 47 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000); 48 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000); 49 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000); 50 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000); 51 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000); 52 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000); 53 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000); 54 55 mmio_write_32(DDRSGRF_BASE + FIREWALL_DDR_FW_DDR_CON_REG, 0xffff0000); 56 } 57 58 static void set_pll_slow_mode(uint32_t clk_pll) 59 { 60 mmio_write_32(CRU_BASE + CRU_MODE_CON00, 0x03 << (16 + clk_pll * 2)); 61 } 62 63 static void __dead2 soc_global_soft_reset(void) 64 { 65 set_pll_slow_mode(CLK_CPLL); 66 set_pll_slow_mode(CLK_GPLL); 67 set_pll_slow_mode(CLK_NPLL); 68 set_pll_slow_mode(CLK_VPLL); 69 set_pll_slow_mode(CLK_USBPLL); 70 set_pll_slow_mode(CLK_APLL); 71 mmio_write_32(PMUCRU_BASE + PMUCRU_MODE_CON00, 0x000f0000); 72 73 dsb(); 74 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 75 /* 76 * Maybe the HW needs some times to reset the system, 77 * so we do not hope the core to excute valid codes. 78 */ 79 while (1) { 80 ; 81 } 82 } 83 84 static void rockchip_system_reset_init(void) 85 { 86 mmio_write_32(GRF_BASE + 0x0508, 0x00100010); 87 mmio_write_32(CRU_BASE + 0x00dc, 0x01030103); 88 } 89 90 void __dead2 rockchip_soc_soft_reset(void) 91 { 92 soc_global_soft_reset(); 93 } 94 95 void plat_rockchip_soc_init(void) 96 { 97 secure_timer_init(); 98 sgrf_init(); 99 rockchip_system_reset_init(); 100 NOTICE("BL31: Rockchip release version: v%d.%d\n", 101 MAJOR_VERSION, MINOR_VERSION); 102 } 103 104