1 /* 2 * Copyright (c) 2023-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/xlat_tables/xlat_tables_v2.h> 9 #include <mmio.h> 10 #include <platform_def.h> 11 12 #include <plat_private.h> 13 #include <rk3568_clk.h> 14 #include <soc.h> 15 16 const mmap_region_t plat_rk_mmap[] = { 17 MAP_REGION_FLAT(RKFPGA_DEV_RNG0_BASE, RKFPGA_DEV_RNG0_SIZE, 18 MT_DEVICE | MT_RW | MT_SECURE), 19 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 20 MT_MEMORY | MT_RW | MT_SECURE), 21 MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE, 22 MT_DEVICE | MT_RW | MT_NS), 23 24 { 0 } 25 }; 26 27 /* The RockChip power domain tree descriptor */ 28 const unsigned char rockchip_power_domain_tree_desc[] = { 29 /* No of root nodes */ 30 PLATFORM_SYSTEM_COUNT, 31 /* No of children for the root node */ 32 PLATFORM_CLUSTER_COUNT, 33 /* No of children for the first cluster node */ 34 PLATFORM_CLUSTER0_CORE_COUNT, 35 }; 36 37 static void secure_timer_init(void) 38 { 39 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS); 40 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 41 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 42 43 /* auto reload & enable the timer */ 44 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); 45 } 46 47 static void sgrf_init(void) 48 { 49 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000); 50 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000); 51 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000); 52 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000); 53 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000); 54 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000); 55 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000); 56 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000); 57 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000); 58 59 mmio_write_32(DDRSGRF_BASE + FIREWALL_DDR_FW_DDR_CON_REG, 0xffff0000); 60 } 61 62 static void set_pll_slow_mode(uint32_t clk_pll) 63 { 64 mmio_write_32(CRU_BASE + CRU_MODE_CON00, 0x03 << (16 + clk_pll * 2)); 65 } 66 67 static void __dead2 soc_global_soft_reset(void) 68 { 69 set_pll_slow_mode(CLK_CPLL); 70 set_pll_slow_mode(CLK_GPLL); 71 set_pll_slow_mode(CLK_NPLL); 72 set_pll_slow_mode(CLK_VPLL); 73 set_pll_slow_mode(CLK_USBPLL); 74 set_pll_slow_mode(CLK_APLL); 75 mmio_write_32(PMUCRU_BASE + PMUCRU_MODE_CON00, 0x000f0000); 76 77 dsb(); 78 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 79 /* 80 * Maybe the HW needs some times to reset the system, 81 * so we do not hope the core to excute valid codes. 82 */ 83 while (1) { 84 ; 85 } 86 } 87 88 static void rockchip_system_reset_init(void) 89 { 90 mmio_write_32(GRF_BASE + 0x0508, 0x00100010); 91 mmio_write_32(CRU_BASE + 0x00dc, 0x01030103); 92 } 93 94 void __dead2 rockchip_soc_soft_reset(void) 95 { 96 soc_global_soft_reset(); 97 } 98 99 void plat_rockchip_soc_init(void) 100 { 101 rockchip_clock_init(); 102 secure_timer_init(); 103 sgrf_init(); 104 rockchip_system_reset_init(); 105 rockchip_init_scmi_server(); 106 NOTICE("BL31: Rockchip release version: v%d.%d\n", 107 MAJOR_VERSION, MINOR_VERSION); 108 } 109 110