1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_DEF_H__ 32 #define __PLAT_DEF_H__ 33 34 #define RK3399_PRIMARY_CPU 0x0 35 36 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 37 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 38 39 #define SIZE_K(n) ((n) * 1024) 40 #define SIZE_M(n) ((n) * 1024 * 1024) 41 42 #define CCI500_BASE 0xffb00000 43 #define CCI500_SIZE SIZE_M(1) 44 45 #define GIC500_BASE 0xfee00000 46 #define GIC500_SIZE SIZE_M(2) 47 48 #define STIME_BASE 0xff860000 49 #define STIME_SIZE SIZE_K(64) 50 51 #define CRUS_BASE 0xff750000 52 #define CRUS_SIZE SIZE_K(128) 53 54 #define SGRF_BASE 0xff330000 55 #define SGRF_SIZE SIZE_K(64) 56 57 #define PMU_BASE 0xff310000 58 #define PMU_SIZE SIZE_K(64) 59 60 #define PMUSRAM_BASE 0xff3b0000 61 #define PMUSRAM_SIZE SIZE_K(64) 62 #define PMUSRAM_RSIZE SIZE_K(8) 63 64 #define PMUGRF_BASE 0xff320000 65 #define PMUGRF_SIZE SIZE_K(64) 66 67 #define GPIO0_BASE 0xff720000 68 #define GPIO0_SIZE SIZE_K(64) 69 70 #define GPIO1_BASE 0xff730000 71 #define GPIO1_SIZE SIZE_K(64) 72 73 #define GPIO2_BASE 0xff780000 74 #define GPIO2_SIZE SIZE_K(32) 75 76 #define GPIO3_BASE 0xff788000 77 #define GPIO3_SIZE SIZE_K(32) 78 79 #define GPIO4_BASE 0xff790000 80 #define GPIO4_SIZE SIZE_K(32) 81 82 #define GRF_BASE 0xff770000 83 #define GRF_SIZE SIZE_K(64) 84 85 #define SERVICE_NOC_0_BASE 0xffa50000 86 #define NOC_0_SIZE SIZE_K(192) 87 88 #define SERVICE_NOC_1_BASE 0xffa84000 89 #define NOC_1_SIZE SIZE_K(16) 90 91 #define SERVICE_NOC_2_BASE 0xffa8c000 92 #define NOC_2_SIZE SIZE_K(16) 93 94 #define SERVICE_NOC_3_BASE 0xffa90000 95 #define NOC_3_SIZE SIZE_K(448) 96 97 /* 98 * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr 99 * 0xff650000 -0xff6c0000 100 */ 101 #define PD_BUS0_BASE 0xff650000 102 #define PD_BUS0_SIZE 0x70000 103 104 #define PMUCRU_BASE 0xff750000 105 #define CRU_BASE 0xff760000 106 107 #define COLD_BOOT_BASE 0xffff0000 108 109 /************************************************************************** 110 * UART related constants 111 **************************************************************************/ 112 #define RK3399_UART2_BASE (0xff1a0000) 113 #define RK3399_UART2_SIZE SIZE_K(64) 114 115 #define RK3399_BAUDRATE (115200) 116 #define RK3399_UART_CLOCK (24000000) 117 118 /****************************************************************************** 119 * System counter frequency related constants 120 ******************************************************************************/ 121 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 122 123 /* Base rockchip_platform compatible GIC memory map */ 124 #define BASE_GICD_BASE (GIC500_BASE) 125 #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 126 127 /***************************************************************************** 128 * CCI-400 related constants 129 ******************************************************************************/ 130 #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 131 #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 132 133 /****************************************************************************** 134 * sgi, ppi 135 ******************************************************************************/ 136 #define ARM_IRQ_SEC_PHY_TIMER 29 137 138 #define ARM_IRQ_SEC_SGI_0 8 139 #define ARM_IRQ_SEC_SGI_1 9 140 #define ARM_IRQ_SEC_SGI_2 10 141 #define ARM_IRQ_SEC_SGI_3 11 142 #define ARM_IRQ_SEC_SGI_4 12 143 #define ARM_IRQ_SEC_SGI_5 13 144 #define ARM_IRQ_SEC_SGI_6 14 145 #define ARM_IRQ_SEC_SGI_7 15 146 /* 147 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 148 * terminology. On a GICv2 system or mode, the lists will be merged and treated 149 * as Group 0 interrupts. 150 */ 151 #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER 152 #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 153 154 #endif /* __PLAT_DEF_H__ */ 155