1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_DEF_H__ 32 #define __PLAT_DEF_H__ 33 34 #include <addressmap.h> 35 36 #define RK3399_PRIMARY_CPU 0x0 37 38 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 39 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 40 41 /************************************************************************** 42 * UART related constants 43 **************************************************************************/ 44 #define RK3399_BAUDRATE 115200 45 #define RK3399_UART_CLOCK 24000000 46 47 /****************************************************************************** 48 * System counter frequency related constants 49 ******************************************************************************/ 50 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 51 52 /* Base rockchip_platform compatible GIC memory map */ 53 #define BASE_GICD_BASE (GIC500_BASE) 54 #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 55 56 /***************************************************************************** 57 * CCI-400 related constants 58 ******************************************************************************/ 59 #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 60 #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 61 62 /****************************************************************************** 63 * sgi, ppi 64 ******************************************************************************/ 65 #define ARM_IRQ_SEC_PHY_TIMER 29 66 67 #define ARM_IRQ_SEC_SGI_0 8 68 #define ARM_IRQ_SEC_SGI_1 9 69 #define ARM_IRQ_SEC_SGI_2 10 70 #define ARM_IRQ_SEC_SGI_3 11 71 #define ARM_IRQ_SEC_SGI_4 12 72 #define ARM_IRQ_SEC_SGI_5 13 73 #define ARM_IRQ_SEC_SGI_6 14 74 #define ARM_IRQ_SEC_SGI_7 15 75 76 /* 77 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 78 * terminology. On a GICv2 system or mode, the lists will be merged and treated 79 * as Group 0 interrupts. 80 */ 81 #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER 82 #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 83 84 #endif /* __PLAT_DEF_H__ */ 85