1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_DEF_H__ 32 #define __PLAT_DEF_H__ 33 34 #define RK3399_PRIMARY_CPU 0x0 35 36 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 37 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 38 39 #define SIZE_K(n) ((n) * 1024) 40 #define SIZE_M(n) ((n) * 1024 * 1024) 41 42 /* Register base address and size */ 43 #define MMIO_BASE 0xfe000000 44 45 #define GIC500_BASE (MMIO_BASE + 0xe00000) 46 #define GIC500_SIZE SIZE_M(2) 47 48 #define PMU_BASE (MMIO_BASE + 0x1310000) 49 #define PMU_SIZE SIZE_K(64) 50 51 #define PMUGRF_BASE (MMIO_BASE + 0x1320000) 52 #define PMUGRF_SIZE SIZE_K(64) 53 54 #define SGRF_BASE (MMIO_BASE + 0x1330000) 55 #define SGRF_SIZE SIZE_K(64) 56 57 #define PMUSRAM_BASE (MMIO_BASE + 0x13b0000) 58 #define PMUSRAM_SIZE SIZE_K(64) 59 #define PMUSRAM_RSIZE SIZE_K(8) 60 61 #define PWM_BASE (MMIO_BASE + 0x1420000) 62 #define PWM_SIZE SIZE_K(64) 63 64 #define CIC_BASE (MMIO_BASE + 0x1620000) 65 #define CIC_SIZE SIZE_K(4) 66 67 #define DCF_BASE (MMIO_BASE + 0x16a0000) 68 #define DCF_SIZE SIZE_K(4) 69 70 #define GPIO0_BASE (MMIO_BASE + 0x1720000) 71 #define GPIO0_SIZE SIZE_K(64) 72 73 #define GPIO1_BASE (MMIO_BASE + 0x1730000) 74 #define GPIO1_SIZE SIZE_K(64) 75 76 #define CRUS_BASE (MMIO_BASE + 0x1750000) 77 #define CRUS_SIZE SIZE_K(128) 78 79 #define GRF_BASE (MMIO_BASE + 0x1770000) 80 #define GRF_SIZE SIZE_K(64) 81 82 #define GPIO2_BASE (MMIO_BASE + 0x1780000) 83 #define GPIO2_SIZE SIZE_K(32) 84 85 #define GPIO3_BASE (MMIO_BASE + 0x1788000) 86 #define GPIO3_SIZE SIZE_K(32) 87 88 #define GPIO4_BASE (MMIO_BASE + 0x1790000) 89 #define GPIO4_SIZE SIZE_K(32) 90 91 #define STIME_BASE (MMIO_BASE + 0x1860000) 92 #define STIME_SIZE SIZE_K(64) 93 94 #define SRAM_BASE (MMIO_BASE + 0x18c0000) 95 #define SRAM_SIZE SIZE_K(192) 96 97 #define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000) 98 #define NOC_0_SIZE SIZE_K(192) 99 100 #define DDRC0_BASE (MMIO_BASE + 0x1a80000) 101 #define DDRC0_SIZE SIZE_K(32) 102 103 #define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000) 104 #define NOC_1_SIZE SIZE_K(16) 105 106 #define DDRC1_BASE (MMIO_BASE + 0x1a88000) 107 #define DDRC1_SIZE SIZE_K(32) 108 109 #define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000) 110 #define NOC_2_SIZE SIZE_K(16) 111 112 #define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000) 113 #define NOC_3_SIZE SIZE_K(448) 114 115 #define CCI500_BASE (MMIO_BASE + 0x1b00000) 116 #define CCI500_SIZE SIZE_M(1) 117 118 #define DDR_PI_OFFSET 0x800 119 #define DDR_PHY_OFFSET 0x2000 120 121 #define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET) 122 #define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET) 123 #define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET) 124 #define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET) 125 126 /* Aggregate of all devices in the first GB */ 127 #define RK3399_DEV_RNG0_BASE MMIO_BASE 128 #define RK3399_DEV_RNG0_SIZE 0x1d00000 129 130 /* 131 * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr 132 * 0xff650000 -0xff6c0000 133 */ 134 #define PD_BUS0_BASE (MMIO_BASE + 0x1650000) 135 #define PD_BUS0_SIZE SIZE_K(448) 136 137 #define PMUCRU_BASE (MMIO_BASE + 0x1750000) 138 #define CRU_BASE (MMIO_BASE + 0x1760000) 139 140 #define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000) 141 142 /************************************************************************** 143 * UART related constants 144 **************************************************************************/ 145 #define RK3399_UART2_BASE (0xff1a0000) 146 #define RK3399_UART2_SIZE SIZE_K(64) 147 148 #define RK3399_BAUDRATE (115200) 149 #define RK3399_UART_CLOCK (24000000) 150 151 /****************************************************************************** 152 * System counter frequency related constants 153 ******************************************************************************/ 154 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 155 156 /* Base rockchip_platform compatible GIC memory map */ 157 #define BASE_GICD_BASE (GIC500_BASE) 158 #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 159 160 /***************************************************************************** 161 * CCI-400 related constants 162 ******************************************************************************/ 163 #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 164 #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 165 166 /****************************************************************************** 167 * sgi, ppi 168 ******************************************************************************/ 169 #define ARM_IRQ_SEC_PHY_TIMER 29 170 171 #define ARM_IRQ_SEC_SGI_0 8 172 #define ARM_IRQ_SEC_SGI_1 9 173 #define ARM_IRQ_SEC_SGI_2 10 174 #define ARM_IRQ_SEC_SGI_3 11 175 #define ARM_IRQ_SEC_SGI_4 12 176 #define ARM_IRQ_SEC_SGI_5 13 177 #define ARM_IRQ_SEC_SGI_6 14 178 #define ARM_IRQ_SEC_SGI_7 15 179 /* 180 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 181 * terminology. On a GICv2 system or mode, the lists will be merged and treated 182 * as Group 0 interrupts. 183 */ 184 #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER 185 #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 186 187 #endif /* __PLAT_DEF_H__ */ 188