16fba6e04STony Xie /* 26fba6e04STony Xie * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 76fba6e04STony Xie #ifndef __PLAT_DEF_H__ 86fba6e04STony Xie #define __PLAT_DEF_H__ 96fba6e04STony Xie 101830f790SXing Zheng #include <addressmap.h> 111830f790SXing Zheng 126fba6e04STony Xie #define RK3399_PRIMARY_CPU 0x0 136fba6e04STony Xie 146fba6e04STony Xie /* Special value used to verify platform parameters from BL2 to BL3-1 */ 156fba6e04STony Xie #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 166fba6e04STony Xie 176fba6e04STony Xie /************************************************************************** 186fba6e04STony Xie * UART related constants 196fba6e04STony Xie **************************************************************************/ 201830f790SXing Zheng #define RK3399_BAUDRATE 115200 211830f790SXing Zheng #define RK3399_UART_CLOCK 24000000 226fba6e04STony Xie 236fba6e04STony Xie /****************************************************************************** 246fba6e04STony Xie * System counter frequency related constants 256fba6e04STony Xie ******************************************************************************/ 266fba6e04STony Xie #define SYS_COUNTER_FREQ_IN_TICKS 24000000 276fba6e04STony Xie 286fba6e04STony Xie /* Base rockchip_platform compatible GIC memory map */ 296fba6e04STony Xie #define BASE_GICD_BASE (GIC500_BASE) 306fba6e04STony Xie #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 316fba6e04STony Xie 326fba6e04STony Xie /***************************************************************************** 336fba6e04STony Xie * CCI-400 related constants 346fba6e04STony Xie ******************************************************************************/ 356fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 366fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 376fba6e04STony Xie 386fba6e04STony Xie /****************************************************************************** 396fba6e04STony Xie * sgi, ppi 406fba6e04STony Xie ******************************************************************************/ 416fba6e04STony Xie #define ARM_IRQ_SEC_PHY_TIMER 29 426fba6e04STony Xie 436fba6e04STony Xie #define ARM_IRQ_SEC_SGI_0 8 446fba6e04STony Xie #define ARM_IRQ_SEC_SGI_1 9 456fba6e04STony Xie #define ARM_IRQ_SEC_SGI_2 10 466fba6e04STony Xie #define ARM_IRQ_SEC_SGI_3 11 476fba6e04STony Xie #define ARM_IRQ_SEC_SGI_4 12 486fba6e04STony Xie #define ARM_IRQ_SEC_SGI_5 13 496fba6e04STony Xie #define ARM_IRQ_SEC_SGI_6 14 506fba6e04STony Xie #define ARM_IRQ_SEC_SGI_7 15 511830f790SXing Zheng 526fba6e04STony Xie /* 536fba6e04STony Xie * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 546fba6e04STony Xie * terminology. On a GICv2 system or mode, the lists will be merged and treated 556fba6e04STony Xie * as Group 0 interrupts. 566fba6e04STony Xie */ 576fba6e04STony Xie #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER 586fba6e04STony Xie #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 596fba6e04STony Xie 606fba6e04STony Xie #endif /* __PLAT_DEF_H__ */ 61