16fba6e04STony Xie /* 26fba6e04STony Xie * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 46fba6e04STony Xie * Redistribution and use in source and binary forms, with or without 56fba6e04STony Xie * modification, are permitted provided that the following conditions are met: 66fba6e04STony Xie * 76fba6e04STony Xie * Redistributions of source code must retain the above copyright notice, this 86fba6e04STony Xie * list of conditions and the following disclaimer. 96fba6e04STony Xie * 106fba6e04STony Xie * Redistributions in binary form must reproduce the above copyright notice, 116fba6e04STony Xie * this list of conditions and the following disclaimer in the documentation 126fba6e04STony Xie * and/or other materials provided with the distribution. 136fba6e04STony Xie * 146fba6e04STony Xie * Neither the name of ARM nor the names of its contributors may be used 156fba6e04STony Xie * to endorse or promote products derived from this software without specific 166fba6e04STony Xie * prior written permission. 176fba6e04STony Xie * 186fba6e04STony Xie * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 196fba6e04STony Xie * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 206fba6e04STony Xie * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 216fba6e04STony Xie * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 226fba6e04STony Xie * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 236fba6e04STony Xie * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 246fba6e04STony Xie * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 256fba6e04STony Xie * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 266fba6e04STony Xie * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 276fba6e04STony Xie * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 286fba6e04STony Xie * POSSIBILITY OF SUCH DAMAGE. 296fba6e04STony Xie */ 306fba6e04STony Xie 316fba6e04STony Xie #ifndef __PLAT_DEF_H__ 326fba6e04STony Xie #define __PLAT_DEF_H__ 336fba6e04STony Xie 34*1830f790SXing Zheng #include <addressmap.h> 35*1830f790SXing Zheng 366fba6e04STony Xie #define RK3399_PRIMARY_CPU 0x0 376fba6e04STony Xie 386fba6e04STony Xie /* Special value used to verify platform parameters from BL2 to BL3-1 */ 396fba6e04STony Xie #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 406fba6e04STony Xie 416fba6e04STony Xie /************************************************************************** 426fba6e04STony Xie * UART related constants 436fba6e04STony Xie **************************************************************************/ 44*1830f790SXing Zheng #define RK3399_BAUDRATE 115200 45*1830f790SXing Zheng #define RK3399_UART_CLOCK 24000000 466fba6e04STony Xie 476fba6e04STony Xie /****************************************************************************** 486fba6e04STony Xie * System counter frequency related constants 496fba6e04STony Xie ******************************************************************************/ 506fba6e04STony Xie #define SYS_COUNTER_FREQ_IN_TICKS 24000000 516fba6e04STony Xie 526fba6e04STony Xie /* Base rockchip_platform compatible GIC memory map */ 536fba6e04STony Xie #define BASE_GICD_BASE (GIC500_BASE) 546fba6e04STony Xie #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 556fba6e04STony Xie 566fba6e04STony Xie /***************************************************************************** 576fba6e04STony Xie * CCI-400 related constants 586fba6e04STony Xie ******************************************************************************/ 596fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 606fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 616fba6e04STony Xie 626fba6e04STony Xie /****************************************************************************** 636fba6e04STony Xie * sgi, ppi 646fba6e04STony Xie ******************************************************************************/ 656fba6e04STony Xie #define ARM_IRQ_SEC_PHY_TIMER 29 666fba6e04STony Xie 676fba6e04STony Xie #define ARM_IRQ_SEC_SGI_0 8 686fba6e04STony Xie #define ARM_IRQ_SEC_SGI_1 9 696fba6e04STony Xie #define ARM_IRQ_SEC_SGI_2 10 706fba6e04STony Xie #define ARM_IRQ_SEC_SGI_3 11 716fba6e04STony Xie #define ARM_IRQ_SEC_SGI_4 12 726fba6e04STony Xie #define ARM_IRQ_SEC_SGI_5 13 736fba6e04STony Xie #define ARM_IRQ_SEC_SGI_6 14 746fba6e04STony Xie #define ARM_IRQ_SEC_SGI_7 15 75*1830f790SXing Zheng 766fba6e04STony Xie /* 776fba6e04STony Xie * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 786fba6e04STony Xie * terminology. On a GICv2 system or mode, the lists will be merged and treated 796fba6e04STony Xie * as Group 0 interrupts. 806fba6e04STony Xie */ 816fba6e04STony Xie #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER 826fba6e04STony Xie #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 836fba6e04STony Xie 846fba6e04STony Xie #endif /* __PLAT_DEF_H__ */ 85