1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, 8 * this list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <debug.h> 28 #include <mmio.h> 29 #include <plat_sip_calls.h> 30 #include <rockchip_sip_svc.h> 31 #include <runtime_svc.h> 32 #include <dram.h> 33 34 #define RK_SIP_DDR_CFG 0x82000008 35 #define DRAM_INIT 0x00 36 #define DRAM_SET_RATE 0x01 37 #define DRAM_ROUND_RATE 0x02 38 #define DRAM_SET_AT_SR 0x03 39 #define DRAM_GET_BW 0x04 40 #define DRAM_GET_RATE 0x05 41 #define DRAM_CLR_IRQ 0x06 42 #define DRAM_SET_PARAM 0x07 43 44 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) 45 { 46 switch (id) { 47 case DRAM_INIT: 48 ddr_init(); 49 break; 50 case DRAM_SET_RATE: 51 return ddr_set_rate((uint32_t)arg0); 52 case DRAM_ROUND_RATE: 53 return ddr_round_rate((uint32_t)arg0); 54 case DRAM_GET_RATE: 55 return ddr_get_rate(); 56 case DRAM_CLR_IRQ: 57 clr_dcf_irq(); 58 break; 59 case DRAM_SET_PARAM: 60 dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); 61 break; 62 default: 63 break; 64 } 65 66 return 0; 67 } 68 69 uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 70 uint64_t x1, 71 uint64_t x2, 72 uint64_t x3, 73 uint64_t x4, 74 void *cookie, 75 void *handle, 76 uint64_t flags) 77 { 78 switch (smc_fid) { 79 case RK_SIP_DDR_CFG: 80 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); 81 default: 82 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 83 SMC_RET1(handle, SMC_UNK); 84 } 85 } 86