1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mmio.h> 33 #include <plat_sip_calls.h> 34 #include <rockchip_sip_svc.h> 35 #include <runtime_svc.h> 36 #include <dfs.h> 37 38 #define RK_SIP_DDR_CFG 0x82000008 39 #define DRAM_INIT 0x00 40 #define DRAM_SET_RATE 0x01 41 #define DRAM_ROUND_RATE 0x02 42 #define DRAM_SET_AT_SR 0x03 43 #define DRAM_GET_BW 0x04 44 #define DRAM_GET_RATE 0x05 45 #define DRAM_CLR_IRQ 0x06 46 #define DRAM_SET_PARAM 0x07 47 48 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) 49 { 50 switch (id) { 51 case DRAM_INIT: 52 ddr_dfs_init(); 53 break; 54 case DRAM_SET_RATE: 55 return ddr_set_rate((uint32_t)arg0); 56 case DRAM_ROUND_RATE: 57 return ddr_round_rate((uint32_t)arg0); 58 case DRAM_GET_RATE: 59 return ddr_get_rate(); 60 case DRAM_CLR_IRQ: 61 clr_dcf_irq(); 62 break; 63 case DRAM_SET_PARAM: 64 dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); 65 break; 66 default: 67 break; 68 } 69 70 return 0; 71 } 72 73 uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 74 uint64_t x1, 75 uint64_t x2, 76 uint64_t x3, 77 uint64_t x4, 78 void *cookie, 79 void *handle, 80 uint64_t flags) 81 { 82 switch (smc_fid) { 83 case RK_SIP_DDR_CFG: 84 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); 85 default: 86 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 87 SMC_RET1(handle, SMC_UNK); 88 } 89 } 90