11760db68SCaesar Wang /* 21760db68SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 31760db68SCaesar Wang * 41760db68SCaesar Wang * Redistribution and use in source and binary forms, with or without 51760db68SCaesar Wang * modification, are permitted provided that the following conditions are met: 61760db68SCaesar Wang * 7*ede939f2SAntonio Nino Diaz * Redistributions of source code must retain the above copyright notice, this 8*ede939f2SAntonio Nino Diaz * list of conditions and the following disclaimer. 91760db68SCaesar Wang * 10*ede939f2SAntonio Nino Diaz * Redistributions in binary form must reproduce the above copyright notice, 111760db68SCaesar Wang * this list of conditions and the following disclaimer in the documentation 121760db68SCaesar Wang * and/or other materials provided with the distribution. 131760db68SCaesar Wang * 14*ede939f2SAntonio Nino Diaz * Neither the name of ARM nor the names of its contributors may be used 15*ede939f2SAntonio Nino Diaz * to endorse or promote products derived from this software without specific 16*ede939f2SAntonio Nino Diaz * prior written permission. 17*ede939f2SAntonio Nino Diaz * 181760db68SCaesar Wang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 191760db68SCaesar Wang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 201760db68SCaesar Wang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 211760db68SCaesar Wang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 221760db68SCaesar Wang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 231760db68SCaesar Wang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 241760db68SCaesar Wang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 251760db68SCaesar Wang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 261760db68SCaesar Wang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 271760db68SCaesar Wang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 281760db68SCaesar Wang * POSSIBILITY OF SUCH DAMAGE. 291760db68SCaesar Wang */ 301760db68SCaesar Wang 311760db68SCaesar Wang #include <debug.h> 321760db68SCaesar Wang #include <mmio.h> 331760db68SCaesar Wang #include <plat_sip_calls.h> 341760db68SCaesar Wang #include <rockchip_sip_svc.h> 351760db68SCaesar Wang #include <runtime_svc.h> 36613038bcSCaesar Wang #include <dfs.h> 37fe877779SCaesar Wang 38a8656400SCaesar Wang #define RK_SIP_DDR_CFG 0x82000008 39a8656400SCaesar Wang #define DRAM_INIT 0x00 40a8656400SCaesar Wang #define DRAM_SET_RATE 0x01 41a8656400SCaesar Wang #define DRAM_ROUND_RATE 0x02 42a8656400SCaesar Wang #define DRAM_SET_AT_SR 0x03 43a8656400SCaesar Wang #define DRAM_GET_BW 0x04 44a8656400SCaesar Wang #define DRAM_GET_RATE 0x05 45a8656400SCaesar Wang #define DRAM_CLR_IRQ 0x06 46a8656400SCaesar Wang #define DRAM_SET_PARAM 0x07 47fe877779SCaesar Wang 48a8656400SCaesar Wang uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) 49fe877779SCaesar Wang { 50fe877779SCaesar Wang switch (id) { 51a8656400SCaesar Wang case DRAM_INIT: 52613038bcSCaesar Wang ddr_dfs_init(); 53fe877779SCaesar Wang break; 54a8656400SCaesar Wang case DRAM_SET_RATE: 55a8656400SCaesar Wang return ddr_set_rate((uint32_t)arg0); 56a8656400SCaesar Wang case DRAM_ROUND_RATE: 57a8656400SCaesar Wang return ddr_round_rate((uint32_t)arg0); 58a8656400SCaesar Wang case DRAM_GET_RATE: 59fe877779SCaesar Wang return ddr_get_rate(); 60a8656400SCaesar Wang case DRAM_CLR_IRQ: 61fe877779SCaesar Wang clr_dcf_irq(); 62fe877779SCaesar Wang break; 63a8656400SCaesar Wang case DRAM_SET_PARAM: 64a8656400SCaesar Wang dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); 65fe877779SCaesar Wang break; 66fe877779SCaesar Wang default: 67fe877779SCaesar Wang break; 68fe877779SCaesar Wang } 69fe877779SCaesar Wang 70fe877779SCaesar Wang return 0; 71fe877779SCaesar Wang } 721760db68SCaesar Wang 731760db68SCaesar Wang uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 741760db68SCaesar Wang uint64_t x1, 751760db68SCaesar Wang uint64_t x2, 761760db68SCaesar Wang uint64_t x3, 771760db68SCaesar Wang uint64_t x4, 781760db68SCaesar Wang void *cookie, 791760db68SCaesar Wang void *handle, 801760db68SCaesar Wang uint64_t flags) 811760db68SCaesar Wang { 821760db68SCaesar Wang switch (smc_fid) { 83a8656400SCaesar Wang case RK_SIP_DDR_CFG: 84fe877779SCaesar Wang SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); 851760db68SCaesar Wang default: 861760db68SCaesar Wang ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 871760db68SCaesar Wang SMC_RET1(handle, SMC_UNK); 881760db68SCaesar Wang } 891760db68SCaesar Wang } 90