11760db68SCaesar Wang /* 21760db68SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 31760db68SCaesar Wang * 41760db68SCaesar Wang * Redistribution and use in source and binary forms, with or without 51760db68SCaesar Wang * modification, are permitted provided that the following conditions are met: 61760db68SCaesar Wang * 71760db68SCaesar Wang * 1. Redistributions of source code must retain the above copyright notice, 81760db68SCaesar Wang * this list of conditions and the following disclaimer. 91760db68SCaesar Wang * 101760db68SCaesar Wang * 2. Redistributions in binary form must reproduce the above copyright notice, 111760db68SCaesar Wang * this list of conditions and the following disclaimer in the documentation 121760db68SCaesar Wang * and/or other materials provided with the distribution. 131760db68SCaesar Wang * 141760db68SCaesar Wang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 151760db68SCaesar Wang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 161760db68SCaesar Wang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 171760db68SCaesar Wang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 181760db68SCaesar Wang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 191760db68SCaesar Wang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 201760db68SCaesar Wang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 211760db68SCaesar Wang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 221760db68SCaesar Wang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 231760db68SCaesar Wang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 241760db68SCaesar Wang * POSSIBILITY OF SUCH DAMAGE. 251760db68SCaesar Wang */ 261760db68SCaesar Wang 271760db68SCaesar Wang #include <debug.h> 281760db68SCaesar Wang #include <mmio.h> 291760db68SCaesar Wang #include <plat_sip_calls.h> 301760db68SCaesar Wang #include <rockchip_sip_svc.h> 311760db68SCaesar Wang #include <runtime_svc.h> 32fe877779SCaesar Wang #include <dram.h> 33fe877779SCaesar Wang 34*a8656400SCaesar Wang #define RK_SIP_DDR_CFG 0x82000008 35*a8656400SCaesar Wang #define DRAM_INIT 0x00 36*a8656400SCaesar Wang #define DRAM_SET_RATE 0x01 37*a8656400SCaesar Wang #define DRAM_ROUND_RATE 0x02 38*a8656400SCaesar Wang #define DRAM_SET_AT_SR 0x03 39*a8656400SCaesar Wang #define DRAM_GET_BW 0x04 40*a8656400SCaesar Wang #define DRAM_GET_RATE 0x05 41*a8656400SCaesar Wang #define DRAM_CLR_IRQ 0x06 42*a8656400SCaesar Wang #define DRAM_SET_PARAM 0x07 43fe877779SCaesar Wang 44*a8656400SCaesar Wang uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) 45fe877779SCaesar Wang { 46fe877779SCaesar Wang switch (id) { 47*a8656400SCaesar Wang case DRAM_INIT: 48fe877779SCaesar Wang ddr_init(); 49fe877779SCaesar Wang break; 50*a8656400SCaesar Wang case DRAM_SET_RATE: 51*a8656400SCaesar Wang return ddr_set_rate((uint32_t)arg0); 52*a8656400SCaesar Wang case DRAM_ROUND_RATE: 53*a8656400SCaesar Wang return ddr_round_rate((uint32_t)arg0); 54*a8656400SCaesar Wang case DRAM_GET_RATE: 55fe877779SCaesar Wang return ddr_get_rate(); 56*a8656400SCaesar Wang case DRAM_CLR_IRQ: 57fe877779SCaesar Wang clr_dcf_irq(); 58fe877779SCaesar Wang break; 59*a8656400SCaesar Wang case DRAM_SET_PARAM: 60*a8656400SCaesar Wang dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); 61fe877779SCaesar Wang break; 62fe877779SCaesar Wang default: 63fe877779SCaesar Wang break; 64fe877779SCaesar Wang } 65fe877779SCaesar Wang 66fe877779SCaesar Wang return 0; 67fe877779SCaesar Wang } 681760db68SCaesar Wang 691760db68SCaesar Wang uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 701760db68SCaesar Wang uint64_t x1, 711760db68SCaesar Wang uint64_t x2, 721760db68SCaesar Wang uint64_t x3, 731760db68SCaesar Wang uint64_t x4, 741760db68SCaesar Wang void *cookie, 751760db68SCaesar Wang void *handle, 761760db68SCaesar Wang uint64_t flags) 771760db68SCaesar Wang { 781760db68SCaesar Wang switch (smc_fid) { 79*a8656400SCaesar Wang case RK_SIP_DDR_CFG: 80fe877779SCaesar Wang SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); 811760db68SCaesar Wang default: 821760db68SCaesar Wang ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 831760db68SCaesar Wang SMC_RET1(handle, SMC_UNK); 841760db68SCaesar Wang } 851760db68SCaesar Wang } 86