11760db68SCaesar Wang /* 21760db68SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 31760db68SCaesar Wang * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 51760db68SCaesar Wang */ 61760db68SCaesar Wang 71760db68SCaesar Wang #include <debug.h> 81760db68SCaesar Wang #include <mmio.h> 91760db68SCaesar Wang #include <plat_sip_calls.h> 101760db68SCaesar Wang #include <rockchip_sip_svc.h> 111760db68SCaesar Wang #include <runtime_svc.h> 12613038bcSCaesar Wang #include <dfs.h> 13fe877779SCaesar Wang 14a8656400SCaesar Wang #define RK_SIP_DDR_CFG 0x82000008 15a8656400SCaesar Wang #define DRAM_INIT 0x00 16a8656400SCaesar Wang #define DRAM_SET_RATE 0x01 17a8656400SCaesar Wang #define DRAM_ROUND_RATE 0x02 18a8656400SCaesar Wang #define DRAM_SET_AT_SR 0x03 19a8656400SCaesar Wang #define DRAM_GET_BW 0x04 20a8656400SCaesar Wang #define DRAM_GET_RATE 0x05 21a8656400SCaesar Wang #define DRAM_CLR_IRQ 0x06 22a8656400SCaesar Wang #define DRAM_SET_PARAM 0x07 23f91b969cSDerek Basehore #define DRAM_SET_ODT_PD 0x08 24fe877779SCaesar Wang 25f91b969cSDerek Basehore uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, 26f91b969cSDerek Basehore uint64_t id, uint64_t arg2) 27fe877779SCaesar Wang { 28fe877779SCaesar Wang switch (id) { 29a8656400SCaesar Wang case DRAM_SET_RATE: 30a8656400SCaesar Wang return ddr_set_rate((uint32_t)arg0); 31a8656400SCaesar Wang case DRAM_ROUND_RATE: 32a8656400SCaesar Wang return ddr_round_rate((uint32_t)arg0); 33a8656400SCaesar Wang case DRAM_GET_RATE: 34fe877779SCaesar Wang return ddr_get_rate(); 35f91b969cSDerek Basehore case DRAM_SET_ODT_PD: 36f91b969cSDerek Basehore dram_set_odt_pd(arg0, arg1, arg2); 37fe877779SCaesar Wang break; 38fe877779SCaesar Wang default: 39fe877779SCaesar Wang break; 40fe877779SCaesar Wang } 41fe877779SCaesar Wang 42fe877779SCaesar Wang return 0; 43fe877779SCaesar Wang } 441760db68SCaesar Wang 451760db68SCaesar Wang uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 461760db68SCaesar Wang uint64_t x1, 471760db68SCaesar Wang uint64_t x2, 481760db68SCaesar Wang uint64_t x3, 491760db68SCaesar Wang uint64_t x4, 501760db68SCaesar Wang void *cookie, 511760db68SCaesar Wang void *handle, 521760db68SCaesar Wang uint64_t flags) 531760db68SCaesar Wang { 541760db68SCaesar Wang switch (smc_fid) { 55a8656400SCaesar Wang case RK_SIP_DDR_CFG: 56f91b969cSDerek Basehore SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); 571760db68SCaesar Wang default: 581760db68SCaesar Wang ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 591760db68SCaesar Wang SMC_RET1(handle, SMC_UNK); 601760db68SCaesar Wang } 611760db68SCaesar Wang } 62