1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_REGS_H__ 32 #define __PMU_REGS_H__ 33 34 #define PMU_WKUP_CFG0 0x00 35 #define PMU_WKUP_CFG1 0x04 36 #define PMU_WKUP_CFG2 0x08 37 #define PMU_WKUP_CFG3 0x0c 38 #define PMU_WKUP_CFG4 0x10 39 #define PMU_PWRDN_CON 0x14 40 #define PMU_PWRDN_ST 0x18 41 #define PMU_PLL_CON 0x1c 42 #define PMU_PWRMODE_CON 0x20 43 #define PMU_SFT_CON 0x24 44 #define PMU_INT_CON 0x28 45 #define PMU_INT_ST 0x2c 46 #define PMU_GPIO0_POS_INT_CON 0x30 47 #define PMU_GPIO0_NEG_INT_CON 0x34 48 #define PMU_GPIO1_POS_INT_CON 0x38 49 #define PMU_GPIO1_NEG_INT_CON 0x3c 50 #define PMU_GPIO0_POS_INT_ST 0x40 51 #define PMU_GPIO0_NEG_INT_ST 0x44 52 #define PMU_GPIO1_POS_INT_ST 0x48 53 #define PMU_GPIO1_NEG_INT_ST 0x4c 54 #define PMU_PWRDN_INTEN 0x50 55 #define PMU_PWRDN_STATUS 0x54 56 #define PMU_WAKEUP_STATUS 0x58 57 #define PMU_BUS_CLR 0x5c 58 #define PMU_BUS_IDLE_REQ 0x60 59 #define PMU_BUS_IDLE_ST 0x64 60 #define PMU_BUS_IDLE_ACK 0x68 61 #define PMU_CCI500_CON 0x6c 62 #define PMU_ADB400_CON 0x70 63 #define PMU_ADB400_ST 0x74 64 #define PMU_POWER_ST 0x78 65 #define PMU_CORE_PWR_ST 0x7c 66 #define PMU_OSC_CNT 0x80 67 #define PMU_PLLLOCK_CNT 0x84 68 #define PMU_PLLRST_CNT 0x88 69 #define PMU_STABLE_CNT 0x8c 70 #define PMU_DDRIO_PWRON_CNT 0x90 71 #define PMU_WAKEUP_RST_CLR_CNT 0x94 72 #define PMU_DDR_SREF_ST 0x98 73 #define PMU_SCU_L_PWRDN_CNT 0x9c 74 #define PMU_SCU_L_PWRUP_CNT 0xa0 75 #define PMU_SCU_B_PWRDN_CNT 0xa4 76 #define PMU_SCU_B_PWRUP_CNT 0xa8 77 #define PMU_GPU_PWRDN_CNT 0xac 78 #define PMU_GPU_PWRUP_CNT 0xb0 79 #define PMU_CENTER_PWRDN_CNT 0xb4 80 #define PMU_CENTER_PWRUP_CNT 0xb8 81 #define PMU_TIMEOUT_CNT 0xbc 82 #define PMU_CPU0APM_CON 0xc0 83 #define PMU_CPU1APM_CON 0xc4 84 #define PMU_CPU2APM_CON 0xc8 85 #define PMU_CPU3APM_CON 0xcc 86 #define PMU_CPU0BPM_CON 0xd0 87 #define PMU_CPU1BPM_CON 0xd4 88 #define PMU_NOC_AUTO_ENA 0xd8 89 #define PMU_PWRDN_CON1 0xdc 90 91 #define PMUGRF_GPIO0A_IOMUX 0x00 92 #define PMUGRF_GPIO1A_IOMUX 0x10 93 #define PMUGRF_GPIO1C_IOMUX 0x18 94 95 #define PMUGRF_GPIO0A6_IOMUX_SHIFT 12 96 #define PMUGRF_GPIO0A6_IOMUX_PWM 0x1 97 #define PMUGRF_GPIO1C3_IOMUX_SHIFT 6 98 #define PMUGRF_GPIO1C3_IOMUX_PWM 0x1 99 100 #define CPU_AXI_QOS_ID_COREID 0x00 101 #define CPU_AXI_QOS_REVISIONID 0x04 102 #define CPU_AXI_QOS_PRIORITY 0x08 103 #define CPU_AXI_QOS_MODE 0x0c 104 #define CPU_AXI_QOS_BANDWIDTH 0x10 105 #define CPU_AXI_QOS_SATURATION 0x14 106 #define CPU_AXI_QOS_EXTCONTROL 0x18 107 #define CPU_AXI_QOS_NUM_REGS 0x07 108 109 #define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000 110 #define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000 111 #define CPU_AXI_DMAC0_QOS_BASE 0xffa64200 112 #define CPU_AXI_DMAC1_QOS_BASE 0xffa64280 113 #define CPU_AXI_DCF_QOS_BASE 0xffa64180 114 #define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100 115 #define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080 116 #define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000 117 #define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300 118 #define CPU_AXI_GIC_QOS_BASE 0xffa78000 119 #define CPU_AXI_SDIO_QOS_BASE 0xffa76000 120 #define CPU_AXI_SDMMC_QOS_BASE 0xffa74000 121 #define CPU_AXI_EMMC_QOS_BASE 0xffa58000 122 #define CPU_AXI_GMAC_QOS_BASE 0xffa5c000 123 #define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000 124 #define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080 125 #define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100 126 #define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180 127 #define CPU_AXI_GPU_QOS_BASE 0xffae0000 128 #define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000 129 #define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000 130 #define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080 131 #define CPU_AXI_RGA_R_QOS_BASE 0xffab0000 132 #define CPU_AXI_RGA_W_QOS_BASE 0xffab0080 133 #define CPU_AXI_IEP_QOS_BASE 0xffa98000 134 #define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000 135 #define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080 136 #define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000 137 #define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000 138 #define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080 139 #define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000 140 #define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080 141 #define CPU_AXI_HDCP_QOS_BASE 0xffa90000 142 #define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080 143 #define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180 144 #define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100 145 146 #define GRF_GPIO2A_IOMUX 0xe000 147 #define GRF_GPIO2B_IOMUX 0xe004 148 #define GRF_GPIO2C_IOMUX 0xe008 149 #define GRF_GPIO2D_IOMUX 0xe00c 150 #define GRF_GPIO3A_IOMUX 0xe010 151 #define GRF_GPIO3B_IOMUX 0xe014 152 #define GRF_GPIO3C_IOMUX 0xe018 153 #define GRF_GPIO3D_IOMUX 0xe01c 154 #define GRF_GPIO4A_IOMUX 0xe020 155 #define GRF_GPIO4B_IOMUX 0xe024 156 #define GRF_GPIO4C_IOMUX 0xe028 157 #define GRF_GPIO4D_IOMUX 0xe02c 158 159 #define GRF_GPIO2A_P 0xe040 160 #define GRF_GPIO2B_P 0xe044 161 #define GRF_GPIO2C_P 0xe048 162 #define GRF_GPIO2D_P 0xe04C 163 #define GRF_GPIO3A_P 0xe050 164 #define GRF_GPIO3B_P 0xe054 165 #define GRF_GPIO3C_P 0xe058 166 #define GRF_GPIO3D_P 0xe05C 167 #define GRF_GPIO4A_P 0xe060 168 #define GRF_GPIO4B_P 0xe064 169 #define GRF_GPIO4C_P 0xe068 170 #define GRF_GPIO4D_P 0xe06C 171 172 #endif /* __PMU_REGS_H__ */ 173