1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_BITS_H__ 32 #define __PMU_BITS_H__ 33 34 enum pmu_powerdomain_id { 35 PD_CPUL0 = 0, 36 PD_CPUL1, 37 PD_CPUL2, 38 PD_CPUL3, 39 PD_CPUB0, 40 PD_CPUB1, 41 PD_SCUL, 42 PD_SCUB, 43 PD_TCPD0, 44 PD_TCPD1, 45 PD_CCI, 46 PD_PERILP, 47 PD_PERIHP, 48 PD_CENTER, 49 PD_VIO, 50 PD_GPU, 51 PD_VCODEC, 52 PD_VDU, 53 PD_RGA, 54 PD_IEP, 55 PD_VO, 56 PD_ISP0 = 22, 57 PD_ISP1, 58 PD_HDCP, 59 PD_GMAC, 60 PD_EMMC, 61 PD_USB3, 62 PD_EDP, 63 PD_GIC, 64 PD_SD, 65 PD_SDIOAUDIO, 66 PD_END 67 }; 68 69 enum powerdomain_state { 70 PMU_POWER_ON = 0, 71 PMU_POWER_OFF, 72 }; 73 74 enum pmu_bus_id { 75 BUS_ID_GPU = 0, 76 BUS_ID_PERILP, 77 BUS_ID_PERIHP, 78 BUS_ID_VCODEC, 79 BUS_ID_VDU, 80 BUS_ID_RGA, 81 BUS_ID_IEP, 82 BUS_ID_VOPB, 83 BUS_ID_VOPL, 84 BUS_ID_ISP0, 85 BUS_ID_ISP1, 86 BUS_ID_HDCP, 87 BUS_ID_USB3, 88 BUS_ID_PERILPM0, 89 BUS_ID_CENTER, 90 BUS_ID_CCIM0, 91 BUS_ID_CCIM1, 92 BUS_ID_VIO, 93 BUS_ID_MSCH0, 94 BUS_ID_MSCH1, 95 BUS_ID_ALIVE, 96 BUS_ID_PMU, 97 BUS_ID_EDP, 98 BUS_ID_GMAC, 99 BUS_ID_EMMC, 100 BUS_ID_CENTER1, 101 BUS_ID_PMUM0, 102 BUS_ID_GIC, 103 BUS_ID_SD, 104 BUS_ID_SDIOAUDIO, 105 }; 106 107 enum pmu_bus_state { 108 BUS_ACTIVE, 109 BUS_IDLE, 110 }; 111 112 /* pmu_cpuapm bit */ 113 enum pmu_cores_pm_by_wfi { 114 core_pm_en = 0, 115 core_pm_int_wakeup_en, 116 core_pm_resv, 117 core_pm_sft_wakeup_en 118 }; 119 120 enum pmu_wkup_cfg0 { 121 PMU_GPIO0A_POSE_WKUP_EN = 0, 122 PMU_GPIO0B_POSE_WKUP_EN = 8, 123 PMU_GPIO0C_POSE_WKUP_EN = 16, 124 PMU_GPIO0D_POSE_WKUP_EN = 24, 125 }; 126 127 enum pmu_wkup_cfg1 { 128 PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, 129 PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, 130 PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, 131 PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, 132 }; 133 134 enum pmu_wkup_cfg2 { 135 PMU_GPIO1A_POSE_WKUP_EN = 0, 136 PMU_GPIO1B_POSE_WKUP_EN = 7, 137 PMU_GPIO1C_POSE_WKUP_EN = 16, 138 PMU_GPIO1D_POSE_WKUP_EN = 24, 139 }; 140 141 enum pmu_wkup_cfg3 { 142 PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, 143 PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, 144 PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, 145 PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, 146 }; 147 148 /* pmu_wkup_cfg4 */ 149 enum pmu_wkup_cfg4 { 150 PMU_CLUSTER_L_WKUP_EN = 0, 151 PMU_CLUSTER_B_WKUP_EN, 152 PMU_GPIO_WKUP_EN, 153 PMU_SDIO_WKUP_EN, 154 155 PMU_SDMMC_WKUP_EN, 156 PMU_TIMER_WKUP_EN = 6, 157 PMU_USBDEV_WKUP_EN, 158 159 PMU_SFT_WKUP_EN, 160 PMU_M0_WDT_WKUP_EN, 161 PMU_TIMEOUT_WKUP_EN, 162 PMU_PWM_WKUP_EN, 163 164 PMU_PCIE_WKUP_EN = 13, 165 }; 166 167 enum pmu_pwrdn_con { 168 PMU_A53_L0_PWRDWN_EN = 0, 169 PMU_A53_L1_PWRDWN_EN, 170 PMU_A53_L2_PWRDWN_EN, 171 PMU_A53_L3_PWRDWN_EN, 172 173 PMU_A72_B0_PWRDWN_EN, 174 PMU_A72_B1_PWRDWN_EN, 175 PMU_SCU_L_PWRDWN_EN, 176 PMU_SCU_B_PWRDWN_EN, 177 178 PMU_TCPD0_PWRDWN_EN, 179 PMU_TCPD1_PWRDWN_EN, 180 PMU_CCI_PWRDWN_EN, 181 PMU_PERILP_PWRDWN_EN, 182 183 PMU_PERIHP_PWRDWN_EN, 184 PMU_CENTER_PWRDWN_EN, 185 PMU_VIO_PWRDWN_EN, 186 PMU_GPU_PWRDWN_EN, 187 188 PMU_VCODEC_PWRDWN_EN, 189 PMU_VDU_PWRDWN_EN, 190 PMU_RGA_PWRDWN_EN, 191 PMU_IEP_PWRDWN_EN, 192 193 PMU_VO_PWRDWN_EN, 194 PMU_ISP0_PWRDWN_EN = 22, 195 PMU_ISP1_PWRDWN_EN, 196 197 PMU_HDCP_PWRDWN_EN, 198 PMU_GMAC_PWRDWN_EN, 199 PMU_EMMC_PWRDWN_EN, 200 PMU_USB3_PWRDWN_EN, 201 202 PMU_EDP_PWRDWN_EN, 203 PMU_GIC_PWRDWN_EN, 204 PMU_SD_PWRDWN_EN, 205 PMU_SDIOAUDIO_PWRDWN_EN, 206 }; 207 208 enum pmu_pwrdn_st { 209 PMU_A53_L0_PWRDWN_ST = 0, 210 PMU_A53_L1_PWRDWN_ST, 211 PMU_A53_L2_PWRDWN_ST, 212 PMU_A53_L3_PWRDWN_ST, 213 214 PMU_A72_B0_PWRDWN_ST, 215 PMU_A72_B1_PWRDWN_ST, 216 PMU_SCU_L_PWRDWN_ST, 217 PMU_SCU_B_PWRDWN_ST, 218 219 PMU_TCPD0_PWRDWN_ST, 220 PMU_TCPD1_PWRDWN_ST, 221 PMU_CCI_PWRDWN_ST, 222 PMU_PERILP_PWRDWN_ST, 223 224 PMU_PERIHP_PWRDWN_ST, 225 PMU_CENTER_PWRDWN_ST, 226 PMU_VIO_PWRDWN_ST, 227 PMU_GPU_PWRDWN_ST, 228 229 PMU_VCODEC_PWRDWN_ST, 230 PMU_VDU_PWRDWN_ST, 231 PMU_RGA_PWRDWN_ST, 232 PMU_IEP_PWRDWN_ST, 233 234 PMU_VO_PWRDWN_ST, 235 PMU_ISP0_PWRDWN_ST = 22, 236 PMU_ISP1_PWRDWN_ST, 237 238 PMU_HDCP_PWRDWN_ST, 239 PMU_GMAC_PWRDWN_ST, 240 PMU_EMMC_PWRDWN_ST, 241 PMU_USB3_PWRDWN_ST, 242 243 PMU_EDP_PWRDWN_ST, 244 PMU_GIC_PWRDWN_ST, 245 PMU_SD_PWRDWN_ST, 246 PMU_SDIOAUDIO_PWRDWN_ST, 247 248 }; 249 250 enum pmu_pll_con { 251 PMU_PLL_PD_CFG = 0, 252 PMU_SFT_PLL_PD = 8, 253 }; 254 255 enum pmu_pwermode_con { 256 PMU_PWR_MODE_EN = 0, 257 PMU_WKUP_RST_EN, 258 PMU_INPUT_CLAMP_EN, 259 PMU_OSC_DIS, 260 261 PMU_ALIVE_USE_LF, 262 PMU_PMU_USE_LF, 263 PMU_POWER_OFF_REQ_CFG, 264 PMU_CHIP_PD_EN, 265 266 PMU_PLL_PD_EN, 267 PMU_CPU0_PD_EN, 268 PMU_L2_FLUSH_EN, 269 PMU_L2_IDLE_EN, 270 271 PMU_SCU_PD_EN, 272 PMU_CCI_PD_EN, 273 PMU_PERILP_PD_EN, 274 PMU_CENTER_PD_EN, 275 276 PMU_SREF0_ENTER_EN, 277 PMU_DDRC0_GATING_EN, 278 PMU_DDRIO0_RET_EN, 279 PMU_DDRIO0_RET_DE_REQ, 280 281 PMU_SREF1_ENTER_EN, 282 PMU_DDRC1_GATING_EN, 283 PMU_DDRIO1_RET_EN, 284 PMU_DDRIO1_RET_DE_REQ, 285 286 PMU_CLK_CENTER_SRC_GATE_EN = 26, 287 PMU_CLK_PERILP_SRC_GATE_EN, 288 289 PMU_CLK_CORE_SRC_GATE_EN, 290 PMU_DDRIO_RET_HW_DE_REQ, 291 PMU_SLP_OUTPUT_CFG, 292 PMU_MAIN_CLUSTER, 293 }; 294 295 enum pmu_sft_con { 296 PMU_WKUP_SFT = 0, 297 PMU_INPUT_CLAMP_CFG, 298 PMU_OSC_DIS_CFG, 299 PMU_PMU_LF_EN_CFG, 300 301 PMU_ALIVE_LF_EN_CFG, 302 PMU_24M_EN_CFG, 303 PMU_DBG_PWRUP_L0_CFG, 304 PMU_WKUP_SFT_M0, 305 306 PMU_DDRCTL0_C_SYSREQ_CFG, 307 PMU_DDR0_IO_RET_CFG, 308 309 PMU_DDRCTL1_C_SYSREQ_CFG = 12, 310 PMU_DDR1_IO_RET_CFG, 311 DBG_PWRUP_B0_CFG = 15, 312 313 DBG_NOPWERDWN_L0_EN, 314 DBG_NOPWERDWN_L1_EN, 315 DBG_NOPWERDWN_L2_EN, 316 DBG_NOPWERDWN_L3_EN, 317 318 DBG_PWRUP_REQ_L_EN = 20, 319 CLUSTER_L_CLK_SRC_GATING_CFG, 320 L2_FLUSH_REQ_CLUSTER_L, 321 ACINACTM_CLUSTER_L_CFG, 322 323 DBG_NO_PWERDWN_B0_EN, 324 DBG_NO_PWERDWN_B1_EN, 325 326 DBG_PWRUP_REQ_B_EN = 28, 327 CLUSTER_B_CLK_SRC_GATING_CFG, 328 L2_FLUSH_REQ_CLUSTER_B, 329 ACINACTM_CLUSTER_B_CFG, 330 }; 331 332 enum pmu_int_con { 333 PMU_PMU_INT_EN = 0, 334 PMU_PWRMD_WKUP_INT_EN, 335 PMU_WKUP_GPIO0_NEG_INT_EN, 336 PMU_WKUP_GPIO0_POS_INT_EN, 337 PMU_WKUP_GPIO1_NEG_INT_EN, 338 PMU_WKUP_GPIO1_POS_INT_EN, 339 }; 340 341 enum pmu_int_st { 342 PMU_PWRMD_WKUP_INT_ST = 1, 343 PMU_WKUP_GPIO0_NEG_INT_ST, 344 PMU_WKUP_GPIO0_POS_INT_ST, 345 PMU_WKUP_GPIO1_NEG_INT_ST, 346 PMU_WKUP_GPIO1_POS_INT_ST, 347 }; 348 349 enum pmu_gpio0_pos_int_con { 350 PMU_GPIO0A_POS_INT_EN = 0, 351 PMU_GPIO0B_POS_INT_EN = 8, 352 PMU_GPIO0C_POS_INT_EN = 16, 353 PMU_GPIO0D_POS_INT_EN = 24, 354 }; 355 356 enum pmu_gpio0_neg_int_con { 357 PMU_GPIO0A_NEG_INT_EN = 0, 358 PMU_GPIO0B_NEG_INT_EN = 8, 359 PMU_GPIO0C_NEG_INT_EN = 16, 360 PMU_GPIO0D_NEG_INT_EN = 24, 361 }; 362 363 enum pmu_gpio1_pos_int_con { 364 PMU_GPIO1A_POS_INT_EN = 0, 365 PMU_GPIO1B_POS_INT_EN = 8, 366 PMU_GPIO1C_POS_INT_EN = 16, 367 PMU_GPIO1D_POS_INT_EN = 24, 368 }; 369 370 enum pmu_gpio1_neg_int_con { 371 PMU_GPIO1A_NEG_INT_EN = 0, 372 PMU_GPIO1B_NEG_INT_EN = 8, 373 PMU_GPIO1C_NEG_INT_EN = 16, 374 PMU_GPIO1D_NEG_INT_EN = 24, 375 }; 376 377 enum pmu_gpio0_pos_int_st { 378 PMU_GPIO0A_POS_INT_ST = 0, 379 PMU_GPIO0B_POS_INT_ST = 8, 380 PMU_GPIO0C_POS_INT_ST = 16, 381 PMU_GPIO0D_POS_INT_ST = 24, 382 }; 383 384 enum pmu_gpio0_neg_int_st { 385 PMU_GPIO0A_NEG_INT_ST = 0, 386 PMU_GPIO0B_NEG_INT_ST = 8, 387 PMU_GPIO0C_NEG_INT_ST = 16, 388 PMU_GPIO0D_NEG_INT_ST = 24, 389 }; 390 391 enum pmu_gpio1_pos_int_st { 392 PMU_GPIO1A_POS_INT_ST = 0, 393 PMU_GPIO1B_POS_INT_ST = 8, 394 PMU_GPIO1C_POS_INT_ST = 16, 395 PMU_GPIO1D_POS_INT_ST = 24, 396 }; 397 398 enum pmu_gpio1_neg_int_st { 399 PMU_GPIO1A_NEG_INT_ST = 0, 400 PMU_GPIO1B_NEG_INT_ST = 8, 401 PMU_GPIO1C_NEG_INT_ST = 16, 402 PMU_GPIO1D_NEG_INT_ST = 24, 403 }; 404 405 /* pmu power down configure register 0x0050 */ 406 enum pmu_pwrdn_inten { 407 PMU_A53_L0_PWR_SWITCH_INT_EN = 0, 408 PMU_A53_L1_PWR_SWITCH_INT_EN, 409 PMU_A53_L2_PWR_SWITCH_INT_EN, 410 PMU_A53_L3_PWR_SWITCH_INT_EN, 411 412 PMU_A72_B0_PWR_SWITCH_INT_EN, 413 PMU_A72_B1_PWR_SWITCH_INT_EN, 414 PMU_SCU_L_PWR_SWITCH_INT_EN, 415 PMU_SCU_B_PWR_SWITCH_INT_EN, 416 417 PMU_TCPD0_PWR_SWITCH_INT_EN, 418 PMU_TCPD1_PWR_SWITCH_INT_EN, 419 PMU_CCI_PWR_SWITCH_INT_EN, 420 PMU_PERILP_PWR_SWITCH_INT_EN, 421 422 PMU_PERIHP_PWR_SWITCH_INT_EN, 423 PMU_CENTER_PWR_SWITCH_INT_EN, 424 PMU_VIO_PWR_SWITCH_INT_EN, 425 PMU_GPU_PWR_SWITCH_INT_EN, 426 427 PMU_VCODEC_PWR_SWITCH_INT_EN, 428 PMU_VDU_PWR_SWITCH_INT_EN, 429 PMU_RGA_PWR_SWITCH_INT_EN, 430 PMU_IEP_PWR_SWITCH_INT_EN, 431 432 PMU_VO_PWR_SWITCH_INT_EN, 433 PMU_ISP0_PWR_SWITCH_INT_EN = 22, 434 PMU_ISP1_PWR_SWITCH_INT_EN, 435 436 PMU_HDCP_PWR_SWITCH_INT_EN, 437 PMU_GMAC_PWR_SWITCH_INT_EN, 438 PMU_EMMC_PWR_SWITCH_INT_EN, 439 PMU_USB3_PWR_SWITCH_INT_EN, 440 441 PMU_EDP_PWR_SWITCH_INT_EN, 442 PMU_GIC_PWR_SWITCH_INT_EN, 443 PMU_SD_PWR_SWITCH_INT_EN, 444 PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, 445 }; 446 447 enum pmu_wkup_status { 448 PMU_WKUP_BY_CLSTER_L_INT = 0, 449 PMU_WKUP_BY_CLSTER_b_INT, 450 PMU_WKUP_BY_GPIO_INT, 451 PMU_WKUP_BY_SDIO_DET, 452 453 PMU_WKUP_BY_SDMMC_DET, 454 PMU_WKUP_BY_TIMER = 6, 455 PMU_WKUP_BY_USBDEV_DET, 456 457 PMU_WKUP_BY_M0_SFT, 458 PMU_WKUP_BY_M0_WDT_INT, 459 PMU_WKUP_BY_TIMEOUT, 460 PMU_WKUP_BY_PWM, 461 462 PMU_WKUP_BY_PCIE = 13, 463 }; 464 465 enum pmu_bus_clr { 466 PMU_CLR_GPU = 0, 467 PMU_CLR_PERILP, 468 PMU_CLR_PERIHP, 469 PMU_CLR_VCODEC, 470 471 PMU_CLR_VDU, 472 PMU_CLR_RGA, 473 PMU_CLR_IEP, 474 PMU_CLR_VOPB, 475 476 PMU_CLR_VOPL, 477 PMU_CLR_ISP0, 478 PMU_CLR_ISP1, 479 PMU_CLR_HDCP, 480 481 PMU_CLR_USB3, 482 PMU_CLR_PERILPM0, 483 PMU_CLR_CENTER, 484 PMU_CLR_CCIM1, 485 486 PMU_CLR_CCIM0, 487 PMU_CLR_VIO, 488 PMU_CLR_MSCH0, 489 PMU_CLR_MSCH1, 490 491 PMU_CLR_ALIVE, 492 PMU_CLR_PMU, 493 PMU_CLR_EDP, 494 PMU_CLR_GMAC, 495 496 PMU_CLR_EMMC, 497 PMU_CLR_CENTER1, 498 PMU_CLR_PMUM0, 499 PMU_CLR_GIC, 500 501 PMU_CLR_SD, 502 PMU_CLR_SDIOAUDIO, 503 }; 504 505 /* PMU bus idle request register */ 506 enum pmu_bus_idle_req { 507 PMU_IDLE_REQ_GPU = 0, 508 PMU_IDLE_REQ_PERILP, 509 PMU_IDLE_REQ_PERIHP, 510 PMU_IDLE_REQ_VCODEC, 511 512 PMU_IDLE_REQ_VDU, 513 PMU_IDLE_REQ_RGA, 514 PMU_IDLE_REQ_IEP, 515 PMU_IDLE_REQ_VOPB, 516 517 PMU_IDLE_REQ_VOPL, 518 PMU_IDLE_REQ_ISP0, 519 PMU_IDLE_REQ_ISP1, 520 PMU_IDLE_REQ_HDCP, 521 522 PMU_IDLE_REQ_USB3, 523 PMU_IDLE_REQ_PERILPM0, 524 PMU_IDLE_REQ_CENTER, 525 PMU_IDLE_REQ_CCIM0, 526 527 PMU_IDLE_REQ_CCIM1, 528 PMU_IDLE_REQ_VIO, 529 PMU_IDLE_REQ_MSCH0, 530 PMU_IDLE_REQ_MSCH1, 531 532 PMU_IDLE_REQ_ALIVE, 533 PMU_IDLE_REQ_PMU, 534 PMU_IDLE_REQ_EDP, 535 PMU_IDLE_REQ_GMAC, 536 537 PMU_IDLE_REQ_EMMC, 538 PMU_IDLE_REQ_CENTER1, 539 PMU_IDLE_REQ_PMUM0, 540 PMU_IDLE_REQ_GIC, 541 542 PMU_IDLE_REQ_SD, 543 PMU_IDLE_REQ_SDIOAUDIO, 544 }; 545 546 /* pmu bus idle status register */ 547 enum pmu_bus_idle_st { 548 PMU_IDLE_ST_GPU = 0, 549 PMU_IDLE_ST_PERILP, 550 PMU_IDLE_ST_PERIHP, 551 PMU_IDLE_ST_VCODEC, 552 553 PMU_IDLE_ST_VDU, 554 PMU_IDLE_ST_RGA, 555 PMU_IDLE_ST_IEP, 556 PMU_IDLE_ST_VOPB, 557 558 PMU_IDLE_ST_VOPL, 559 PMU_IDLE_ST_ISP0, 560 PMU_IDLE_ST_ISP1, 561 PMU_IDLE_ST_HDCP, 562 563 PMU_IDLE_ST_USB3, 564 PMU_IDLE_ST_PERILPM0, 565 PMU_IDLE_ST_CENTER, 566 PMU_IDLE_ST_CCIM0, 567 568 PMU_IDLE_ST_CCIM1, 569 PMU_IDLE_ST_VIO, 570 PMU_IDLE_ST_MSCH0, 571 PMU_IDLE_ST_MSCH1, 572 573 PMU_IDLE_ST_ALIVE, 574 PMU_IDLE_ST_PMU, 575 PMU_IDLE_ST_EDP, 576 PMU_IDLE_ST_GMAC, 577 578 PMU_IDLE_ST_EMMC, 579 PMU_IDLE_ST_CENTER1, 580 PMU_IDLE_ST_PMUM0, 581 PMU_IDLE_ST_GIC, 582 583 PMU_IDLE_ST_SD, 584 PMU_IDLE_ST_SDIOAUDIO, 585 }; 586 587 enum pmu_bus_idle_ack { 588 PMU_IDLE_ACK_GPU = 0, 589 PMU_IDLE_ACK_PERILP, 590 PMU_IDLE_ACK_PERIHP, 591 PMU_IDLE_ACK_VCODEC, 592 593 PMU_IDLE_ACK_VDU, 594 PMU_IDLE_ACK_RGA, 595 PMU_IDLE_ACK_IEP, 596 PMU_IDLE_ACK_VOPB, 597 598 PMU_IDLE_ACK_VOPL, 599 PMU_IDLE_ACK_ISP0, 600 PMU_IDLE_ACK_ISP1, 601 PMU_IDLE_ACK_HDCP, 602 603 PMU_IDLE_ACK_USB3, 604 PMU_IDLE_ACK_PERILPM0, 605 PMU_IDLE_ACK_CENTER, 606 PMU_IDLE_ACK_CCIM0, 607 608 PMU_IDLE_ACK_CCIM1, 609 PMU_IDLE_ACK_VIO, 610 PMU_IDLE_ACK_MSCH0, 611 PMU_IDLE_ACK_MSCH1, 612 613 PMU_IDLE_ACK_ALIVE, 614 PMU_IDLE_ACK_PMU, 615 PMU_IDLE_ACK_EDP, 616 PMU_IDLE_ACK_GMAC, 617 618 PMU_IDLE_ACK_EMMC, 619 PMU_IDLE_ACK_CENTER1, 620 PMU_IDLE_ACK_PMUM0, 621 PMU_IDLE_ACK_GIC, 622 623 PMU_IDLE_ACK_SD, 624 PMU_IDLE_ACK_SDIOAUDIO, 625 }; 626 627 enum pmu_cci500_con { 628 PMU_PREQ_CCI500_CFG_SW = 0, 629 PMU_CLR_PREQ_CCI500_HW, 630 PMU_PSTATE_CCI500_0, 631 PMU_PSTATE_CCI500_1, 632 633 PMU_PSTATE_CCI500_2, 634 PMU_QREQ_CCI500_CFG_SW, 635 PMU_CLR_QREQ_CCI500_HW, 636 PMU_QGATING_CCI500_CFG, 637 638 PMU_PREQ_CCI500_CFG_SW_WMSK = 16, 639 PMU_CLR_PREQ_CCI500_HW_WMSK, 640 PMU_PSTATE_CCI500_0_WMSK, 641 PMU_PSTATE_CCI500_1_WMSK, 642 643 PMU_PSTATE_CCI500_2_WMSK, 644 PMU_QREQ_CCI500_CFG_SW_WMSK, 645 PMU_CLR_QREQ_CCI500_HW_WMSK, 646 PMU_QGATING_CCI500_CFG_WMSK, 647 }; 648 649 enum pmu_adb400_con { 650 PMU_PWRDWN_REQ_CXCS_SW = 0, 651 PMU_PWRDWN_REQ_CORE_L_SW, 652 PMU_PWRDWN_REQ_CORE_L_2GIC_SW, 653 PMU_PWRDWN_REQ_GIC2_CORE_L_SW, 654 655 PMU_PWRDWN_REQ_CORE_B_SW, 656 PMU_PWRDWN_REQ_CORE_B_2GIC_SW, 657 PMU_PWRDWN_REQ_GIC2_CORE_B_SW, 658 659 PMU_CLR_CXCS_HW = 8, 660 PMU_CLR_CORE_L_HW, 661 PMU_CLR_CORE_L_2GIC_HW, 662 PMU_CLR_GIC2_CORE_L_HW, 663 664 PMU_CLR_CORE_B_HW, 665 PMU_CLR_CORE_B_2GIC_HW, 666 PMU_CLR_GIC2_CORE_B_HW, 667 668 PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, 669 PMU_PWRDWN_REQ_CORE_L_SW_WMSK, 670 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, 671 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, 672 673 PMU_PWRDWN_REQ_CORE_B_SW_WMSK, 674 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, 675 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, 676 677 PMU_CLR_CXCS_HW_WMSK = 24, 678 PMU_CLR_CORE_L_HW_WMSK, 679 PMU_CLR_CORE_L_2GIC_HW_WMSK, 680 PMU_CLR_GIC2_CORE_L_HW_WMSK, 681 682 PMU_CLR_CORE_B_HW_WMSK, 683 PMU_CLR_CORE_B_2GIC_HW_WMSK, 684 PMU_CLR_GIC2_CORE_B_HW_WMSK, 685 }; 686 687 enum pmu_adb400_st { 688 PMU_PWRDWN_REQ_CXCS_SW_ST = 0, 689 PMU_PWRDWN_REQ_CORE_L_SW_ST, 690 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, 691 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, 692 693 PMU_PWRDWN_REQ_CORE_B_SW_ST, 694 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, 695 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, 696 697 PMU_CLR_CXCS_HW_ST = 8, 698 PMU_CLR_CORE_L_HW_ST, 699 PMU_CLR_CORE_L_2GIC_HW_ST, 700 PMU_CLR_GIC2_CORE_L_HW_ST, 701 702 PMU_CLR_CORE_B_HW_ST, 703 PMU_CLR_CORE_B_2GIC_HW_ST, 704 PMU_CLR_GIC2_CORE_B_HW_ST, 705 }; 706 707 enum pmu_pwrdn_con1 { 708 PMU_VD_SCU_L_PWRDN_EN = 0, 709 PMU_VD_SCU_B_PWRDN_EN, 710 PMU_VD_CENTER_PWRDN_EN, 711 }; 712 713 enum pmu_core_pwr_st { 714 L2_FLUSHDONE_CLUSTER_L = 0, 715 STANDBY_BY_WFIL2_CLUSTER_L, 716 717 L2_FLUSHDONE_CLUSTER_B = 10, 718 STANDBY_BY_WFIL2_CLUSTER_B, 719 }; 720 721 #endif /* __PMU_BITS_H__ */ 722