1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ 32 #define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ 33 34 /* CRU */ 35 #define CRU_DPLL_CON0 0x40 36 #define CRU_DPLL_CON1 0x44 37 #define CRU_DPLL_CON2 0x48 38 #define CRU_DPLL_CON3 0x4c 39 #define CRU_DPLL_CON4 0x50 40 #define CRU_DPLL_CON5 0x54 41 42 /* CRU_PLL_CON3 */ 43 #define PLL_SLOW_MODE 0 44 #define PLL_NORMAL_MODE 1 45 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) 46 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) 47 48 /* PMU CRU */ 49 #define PMU_CRU_GATEDIS_CON0 0x130 50 51 #endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */ 52