11830f790SXing Zheng /* 21830f790SXing Zheng * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 31830f790SXing Zheng * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 51830f790SXing Zheng */ 61830f790SXing Zheng 7*c3cf06f1SAntonio Nino Diaz #ifndef MISC_REGS_H 8*c3cf06f1SAntonio Nino Diaz #define MISC_REGS_H 91830f790SXing Zheng 101830f790SXing Zheng /* CRU */ 111830f790SXing Zheng #define CRU_DPLL_CON0 0x40 121830f790SXing Zheng #define CRU_DPLL_CON1 0x44 131830f790SXing Zheng #define CRU_DPLL_CON2 0x48 141830f790SXing Zheng #define CRU_DPLL_CON3 0x4c 151830f790SXing Zheng #define CRU_DPLL_CON4 0x50 161830f790SXing Zheng #define CRU_DPLL_CON5 0x54 171830f790SXing Zheng 181830f790SXing Zheng /* CRU_PLL_CON3 */ 191830f790SXing Zheng #define PLL_SLOW_MODE 0 201830f790SXing Zheng #define PLL_NORMAL_MODE 1 211830f790SXing Zheng #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) 221830f790SXing Zheng #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) 231830f790SXing Zheng 241830f790SXing Zheng /* PMU CRU */ 251830f790SXing Zheng #define PMU_CRU_GATEDIS_CON0 0x130 261830f790SXing Zheng 27*c3cf06f1SAntonio Nino Diaz #endif /* MISC_REGS_H */ 28