1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __DRAM_REGS_H__ 32 #define __DRAM_REGS_H__ 33 34 #define CTL_REG_NUM 332 35 #define PHY_REG_NUM 959 36 #define PI_REG_NUM 200 37 38 #define MSCH_ID_COREID 0x0 39 #define MSCH_ID_REVISIONID 0x4 40 #define MSCH_DEVICECONF 0x8 41 #define MSCH_DEVICESIZE 0xc 42 #define MSCH_DDRTIMINGA0 0x10 43 #define MSCH_DDRTIMINGB0 0x14 44 #define MSCH_DDRTIMINGC0 0x18 45 #define MSCH_DEVTODEV0 0x1c 46 #define MSCH_DDRMODE 0x110 47 #define MSCH_AGINGX0 0x1000 48 49 #define CIC_CTRL0 0x0 50 #define CIC_CTRL1 0x4 51 #define CIC_IDLE_TH 0x8 52 #define CIC_CG_WAIT_TH 0xc 53 #define CIC_STATUS0 0x10 54 #define CIC_STATUS1 0x14 55 #define CIC_CTRL2 0x18 56 #define CIC_CTRL3 0x1c 57 #define CIC_CTRL4 0x20 58 59 /* DENALI_CTL_00 */ 60 #define START 1 61 62 /* DENALI_CTL_68 */ 63 #define PWRUP_SREFRESH_EXIT (1 << 16) 64 65 /* DENALI_CTL_274 */ 66 #define MEM_RST_VALID 1 67 68 #define PHY_DRV_ODT_Hi_Z 0x0 69 #define PHY_DRV_ODT_240 0x1 70 #define PHY_DRV_ODT_120 0x8 71 #define PHY_DRV_ODT_80 0x9 72 #define PHY_DRV_ODT_60 0xc 73 #define PHY_DRV_ODT_48 0xd 74 #define PHY_DRV_ODT_40 0xe 75 #define PHY_DRV_ODT_34_3 0xf 76 77 /* 78 * sys_reg bitfield struct 79 * [31] row_3_4_ch1 80 * [30] row_3_4_ch0 81 * [29:28] chinfo 82 * [27] rank_ch1 83 * [26:25] col_ch1 84 * [24] bk_ch1 85 * [23:22] cs0_row_ch1 86 * [21:20] cs1_row_ch1 87 * [19:18] bw_ch1 88 * [17:16] dbw_ch1; 89 * [15:13] ddrtype 90 * [12] channelnum 91 * [11] rank_ch0 92 * [10:9] col_ch0 93 * [8] bk_ch0 94 * [7:6] cs0_row_ch0 95 * [5:4] cs1_row_ch0 96 * [3:2] bw_ch0 97 * [1:0] dbw_ch0 98 */ 99 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 100 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 101 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 102 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) 103 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 104 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 105 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 106 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 107 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) 108 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) 109 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) 110 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) 111 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) 112 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) 113 #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16)) 114 #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3)) 115 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16)) 116 #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3)) 117 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) 118 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3)) 119 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16)) 120 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3)) 121 #define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \ 122 (0x1f<<(10+16))|((n)<<10)) 123 124 #endif /* __DRAM_REGS_H__ */ 125