1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ 32 #define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ 33 34 #define SIZE_K(n) ((n) * 1024) 35 #define SIZE_M(n) ((n) * 1024 * 1024) 36 37 /* 38 * The parts of the shared defined registers address with AP and M0, 39 * let's note and mark the previous defines like this: 40 */ 41 #define GIC500_BASE (MMIO_BASE + 0x06E00000) 42 #define UART0_BASE (MMIO_BASE + 0x07180000) 43 #define UART1_BASE (MMIO_BASE + 0x07190000) 44 #define UART2_BASE (MMIO_BASE + 0x071A0000) 45 #define UART3_BASE (MMIO_BASE + 0x071B0000) 46 47 #define PMU_BASE (MMIO_BASE + 0x07310000) 48 #define PMUGRF_BASE (MMIO_BASE + 0x07320000) 49 #define SGRF_BASE (MMIO_BASE + 0x07330000) 50 #define PMUSRAM_BASE (MMIO_BASE + 0x073B0000) 51 #define PWM_BASE (MMIO_BASE + 0x07420000) 52 53 #define CIC_BASE (MMIO_BASE + 0x07620000) 54 #define PD_BUS0_BASE (MMIO_BASE + 0x07650000) 55 #define DCF_BASE (MMIO_BASE + 0x076A0000) 56 #define GPIO0_BASE (MMIO_BASE + 0x07720000) 57 #define GPIO1_BASE (MMIO_BASE + 0x07730000) 58 #define PMUCRU_BASE (MMIO_BASE + 0x07750000) 59 #define CRU_BASE (MMIO_BASE + 0x07760000) 60 #define GRF_BASE (MMIO_BASE + 0x07770000) 61 #define GPIO2_BASE (MMIO_BASE + 0x07780000) 62 #define GPIO3_BASE (MMIO_BASE + 0x07788000) 63 #define GPIO4_BASE (MMIO_BASE + 0x07790000) 64 #define STIME_BASE (MMIO_BASE + 0x07860000) 65 #define SRAM_BASE (MMIO_BASE + 0x078C0000) 66 #define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000) 67 #define DDRC0_BASE (MMIO_BASE + 0x07A80000) 68 #define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000) 69 #define DDRC1_BASE (MMIO_BASE + 0x07A88000) 70 #define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000) 71 #define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000) 72 #define CCI500_BASE (MMIO_BASE + 0x07B00000) 73 #define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000) 74 75 /* Registers size */ 76 #define GIC500_SIZE SIZE_M(2) 77 #define UART0_SIZE SIZE_K(64) 78 #define UART1_SIZE SIZE_K(64) 79 #define UART2_SIZE SIZE_K(64) 80 #define UART3_SIZE SIZE_K(64) 81 #define PMU_SIZE SIZE_K(64) 82 #define PMUGRF_SIZE SIZE_K(64) 83 #define SGRF_SIZE SIZE_K(64) 84 #define PMUSRAM_SIZE SIZE_K(64) 85 #define PMUSRAM_RSIZE SIZE_K(8) 86 #define PWM_SIZE SIZE_K(64) 87 #define CIC_SIZE SIZE_K(4) 88 #define DCF_SIZE SIZE_K(4) 89 #define GPIO0_SIZE SIZE_K(64) 90 #define GPIO1_SIZE SIZE_K(64) 91 #define PMUCRU_SIZE SIZE_K(64) 92 #define CRU_SIZE SIZE_K(64) 93 #define GRF_SIZE SIZE_K(64) 94 #define GPIO2_SIZE SIZE_K(32) 95 #define GPIO3_SIZE SIZE_K(32) 96 #define GPIO4_SIZE SIZE_K(32) 97 #define STIME_SIZE SIZE_K(64) 98 #define SRAM_SIZE SIZE_K(192) 99 #define SERVICE_NOC_0_SIZE SIZE_K(192) 100 #define DDRC0_SIZE SIZE_K(32) 101 #define SERVICE_NOC_1_SIZE SIZE_K(16) 102 #define DDRC1_SIZE SIZE_K(32) 103 #define SERVICE_NOC_2_SIZE SIZE_K(16) 104 #define SERVICE_NOC_3_SIZE SIZE_K(448) 105 #define CCI500_SIZE SIZE_M(1) 106 #define PD_BUS0_SIZE SIZE_K(448) 107 108 /* DDR Registers address */ 109 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) 110 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) 111 112 #define PI_OFFSET 0x800 113 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) 114 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) 115 116 #define PHY_OFFSET 0x2000 117 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) 118 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) 119 120 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) 121 122 #endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */ 123