1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arch.h> 35 #include <common_def.h> 36 #include <rk3399_def.h> 37 38 #define DEBUG_XLAT_TABLE 0 39 40 /******************************************************************************* 41 * Platform binary types for linking 42 ******************************************************************************/ 43 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 44 #define PLATFORM_LINKER_ARCH aarch64 45 46 /******************************************************************************* 47 * Generic platform constants 48 ******************************************************************************/ 49 50 /* Size of cacheable stacks */ 51 #if DEBUG_XLAT_TABLE 52 #define PLATFORM_STACK_SIZE 0x800 53 #elif IMAGE_BL1 54 #define PLATFORM_STACK_SIZE 0x440 55 #elif IMAGE_BL2 56 #define PLATFORM_STACK_SIZE 0x400 57 #elif IMAGE_BL31 58 #define PLATFORM_STACK_SIZE 0x800 59 #elif IMAGE_BL32 60 #define PLATFORM_STACK_SIZE 0x440 61 #endif 62 63 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 64 65 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 66 #define PLATFORM_SYSTEM_COUNT 1 67 #define PLATFORM_CLUSTER_COUNT 2 68 #define PLATFORM_CLUSTER0_CORE_COUNT 4 69 #define PLATFORM_CLUSTER1_CORE_COUNT 2 70 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 71 PLATFORM_CLUSTER0_CORE_COUNT) 72 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 73 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 74 PLATFORM_CLUSTER_COUNT + \ 75 PLATFORM_CORE_COUNT) 76 77 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 78 79 /* 80 * This macro defines the deepest retention state possible. A higher state 81 * id will represent an invalid or a power down state. 82 */ 83 #define PLAT_MAX_RET_STATE 1 84 85 /* 86 * This macro defines the deepest power down states possible. Any state ID 87 * higher than this is invalid. 88 */ 89 #define PLAT_MAX_OFF_STATE 2 90 91 /******************************************************************************* 92 * Platform memory map related constants 93 ******************************************************************************/ 94 /* TF txet, ro, rw, Size: 512KB */ 95 #define TZRAM_BASE (0x0) 96 #define TZRAM_SIZE (0x80000) 97 98 /******************************************************************************* 99 * BL31 specific defines. 100 ******************************************************************************/ 101 /* 102 * Put BL3-1 at the top of the Trusted RAM 103 */ 104 #define BL31_BASE (TZRAM_BASE + 0x10000) 105 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 106 107 /******************************************************************************* 108 * Platform specific page table and MMU setup constants 109 ******************************************************************************/ 110 #define ADDR_SPACE_SIZE (1ull << 32) 111 #define MAX_XLAT_TABLES 20 112 #define MAX_MMAP_REGIONS 16 113 114 /******************************************************************************* 115 * Declarations and constants to access the mailboxes safely. Each mailbox is 116 * aligned on the biggest cache line size in the platform. This is known only 117 * to the platform as it might have a combination of integrated and external 118 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 119 * line at any cache level. They could belong to different cpus/clusters & 120 * get written while being protected by different locks causing corruption of 121 * a valid mailbox address. 122 ******************************************************************************/ 123 #define CACHE_WRITEBACK_SHIFT 6 124 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 125 126 /* 127 * Define GICD and GICC and GICR base 128 */ 129 #define PLAT_RK_GICD_BASE BASE_GICD_BASE 130 #define PLAT_RK_GICR_BASE BASE_GICR_BASE 131 #define PLAT_RK_GICC_BASE 0 132 133 /* 134 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 135 * terminology. On a GICv2 system or mode, the lists will be merged and treated 136 * as Group 0 interrupts. 137 */ 138 #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS 139 #define PLAT_RK_G0_IRQS RK3399_G0_IRQS 140 141 #define PLAT_RK_UART_BASE RK3399_UART2_BASE 142 #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 143 #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 144 145 #define PLAT_RK_CCI_BASE CCI500_BASE 146 147 #define PLAT_RK_PRIMARY_CPU 0x0 148 149 #define RK_PLAT_AARCH_CFG RK_PLAT_CFG1 150 151 #endif /* __PLATFORM_DEF_H__ */ 152