1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <bl31_param.h> 12 #include <common_def.h> 13 #include <rk3399_def.h> 14 #include <utils_def.h> 15 16 #define DEBUG_XLAT_TABLE 0 17 18 /******************************************************************************* 19 * Platform binary types for linking 20 ******************************************************************************/ 21 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 22 #define PLATFORM_LINKER_ARCH aarch64 23 24 /******************************************************************************* 25 * Generic platform constants 26 ******************************************************************************/ 27 28 /* Size of cacheable stacks */ 29 #if DEBUG_XLAT_TABLE 30 #define PLATFORM_STACK_SIZE 0x800 31 #elif defined(IMAGE_BL1) 32 #define PLATFORM_STACK_SIZE 0x440 33 #elif defined(IMAGE_BL2) 34 #define PLATFORM_STACK_SIZE 0x400 35 #elif defined(IMAGE_BL31) 36 #define PLATFORM_STACK_SIZE 0x800 37 #elif defined(IMAGE_BL32) 38 #define PLATFORM_STACK_SIZE 0x440 39 #endif 40 41 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 42 43 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 44 #define PLATFORM_SYSTEM_COUNT 1 45 #define PLATFORM_CLUSTER_COUNT 2 46 #define PLATFORM_CLUSTER0_CORE_COUNT 4 47 #define PLATFORM_CLUSTER1_CORE_COUNT 2 48 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 49 PLATFORM_CLUSTER0_CORE_COUNT) 50 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 51 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 52 PLATFORM_CLUSTER_COUNT + \ 53 PLATFORM_CORE_COUNT) 54 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 55 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 56 57 /* 58 * This macro defines the deepest retention state possible. A higher state 59 * id will represent an invalid or a power down state. 60 */ 61 #define PLAT_MAX_RET_STATE U(1) 62 63 /* 64 * This macro defines the deepest power down states possible. Any state ID 65 * higher than this is invalid. 66 */ 67 #define PLAT_MAX_OFF_STATE U(2) 68 69 /******************************************************************************* 70 * Platform specific page table and MMU setup constants 71 ******************************************************************************/ 72 #define ADDR_SPACE_SIZE (1ULL << 32) 73 #define MAX_XLAT_TABLES 20 74 #define MAX_MMAP_REGIONS 25 75 76 /******************************************************************************* 77 * Declarations and constants to access the mailboxes safely. Each mailbox is 78 * aligned on the biggest cache line size in the platform. This is known only 79 * to the platform as it might have a combination of integrated and external 80 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 81 * line at any cache level. They could belong to different cpus/clusters & 82 * get written while being protected by different locks causing corruption of 83 * a valid mailbox address. 84 ******************************************************************************/ 85 #define CACHE_WRITEBACK_SHIFT 6 86 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 87 88 /* 89 * Define GICD and GICC and GICR base 90 */ 91 #define PLAT_RK_GICD_BASE BASE_GICD_BASE 92 #define PLAT_RK_GICR_BASE BASE_GICR_BASE 93 #define PLAT_RK_GICC_BASE 0 94 95 /* 96 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 97 * terminology. On a GICv2 system or mode, the lists will be merged and treated 98 * as Group 0 interrupts. 99 */ 100 #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS 101 #define PLAT_RK_G0_IRQS RK3399_G0_IRQS 102 103 #define PLAT_RK_UART_BASE UART2_BASE 104 #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 105 #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 106 107 #define PLAT_RK_CCI_BASE CCI500_BASE 108 109 #define PLAT_RK_PRIMARY_CPU 0x0 110 111 #define PSRAM_DO_DDR_RESUME 1 112 #define PSRAM_CHECK_WAKEUP_CPU 0 113 114 #endif /* PLATFORM_DEF_H */ 115