1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arch.h> 35 #include <bl31_param.h> 36 #include <common_def.h> 37 #include <rk3399_def.h> 38 39 #define DEBUG_XLAT_TABLE 0 40 41 /******************************************************************************* 42 * Platform binary types for linking 43 ******************************************************************************/ 44 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 45 #define PLATFORM_LINKER_ARCH aarch64 46 47 /******************************************************************************* 48 * Generic platform constants 49 ******************************************************************************/ 50 51 /* Size of cacheable stacks */ 52 #if DEBUG_XLAT_TABLE 53 #define PLATFORM_STACK_SIZE 0x800 54 #elif defined(IMAGE_BL1) 55 #define PLATFORM_STACK_SIZE 0x440 56 #elif defined(IMAGE_BL2) 57 #define PLATFORM_STACK_SIZE 0x400 58 #elif defined(IMAGE_BL31) 59 #define PLATFORM_STACK_SIZE 0x800 60 #elif defined(IMAGE_BL32) 61 #define PLATFORM_STACK_SIZE 0x440 62 #endif 63 64 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 65 66 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 67 #define PLATFORM_SYSTEM_COUNT 1 68 #define PLATFORM_CLUSTER_COUNT 2 69 #define PLATFORM_CLUSTER0_CORE_COUNT 4 70 #define PLATFORM_CLUSTER1_CORE_COUNT 2 71 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 72 PLATFORM_CLUSTER0_CORE_COUNT) 73 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 74 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 75 PLATFORM_CLUSTER_COUNT + \ 76 PLATFORM_CORE_COUNT) 77 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 78 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 79 80 /* 81 * This macro defines the deepest retention state possible. A higher state 82 * id will represent an invalid or a power down state. 83 */ 84 #define PLAT_MAX_RET_STATE 1 85 86 /* 87 * This macro defines the deepest power down states possible. Any state ID 88 * higher than this is invalid. 89 */ 90 #define PLAT_MAX_OFF_STATE 2 91 92 /******************************************************************************* 93 * Platform specific page table and MMU setup constants 94 ******************************************************************************/ 95 #define ADDR_SPACE_SIZE (1ull << 32) 96 #define MAX_XLAT_TABLES 20 97 #define MAX_MMAP_REGIONS 25 98 99 /******************************************************************************* 100 * Declarations and constants to access the mailboxes safely. Each mailbox is 101 * aligned on the biggest cache line size in the platform. This is known only 102 * to the platform as it might have a combination of integrated and external 103 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 104 * line at any cache level. They could belong to different cpus/clusters & 105 * get written while being protected by different locks causing corruption of 106 * a valid mailbox address. 107 ******************************************************************************/ 108 #define CACHE_WRITEBACK_SHIFT 6 109 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 110 111 /* 112 * Define GICD and GICC and GICR base 113 */ 114 #define PLAT_RK_GICD_BASE BASE_GICD_BASE 115 #define PLAT_RK_GICR_BASE BASE_GICR_BASE 116 #define PLAT_RK_GICC_BASE 0 117 118 /* 119 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 120 * terminology. On a GICv2 system or mode, the lists will be merged and treated 121 * as Group 0 interrupts. 122 */ 123 #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS 124 #define PLAT_RK_G0_IRQS RK3399_G0_IRQS 125 126 #define PLAT_RK_UART_BASE UART2_BASE 127 #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 128 #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 129 130 #define PLAT_RK_CCI_BASE CCI500_BASE 131 132 #define PLAT_RK_PRIMARY_CPU 0x0 133 134 #endif /* __PLATFORM_DEF_H__ */ 135