1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#ifndef __ROCKCHIP_PLAT_LD_S__ 7#define __ROCKCHIP_PLAT_LD_S__ 8 9MEMORY { 10 SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 11 PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 12} 13 14SECTIONS 15{ 16 . = SRAM_BASE; 17 ASSERT(. == ALIGN(4096), 18 "SRAM_BASE address is not aligned on a page boundary.") 19 20 /* 21 * The SRAM space allocation for RK3399 22 * ---------------- 23 * | m0 code bin 24 * ---------------- 25 * | sram text 26 * ---------------- 27 * | sram data 28 * ---------------- 29 */ 30 .incbin_sram : ALIGN(4096) { 31 __sram_incbin_start = .; 32 *(.sram.incbin) 33 . = ALIGN(4096); 34 __sram_incbin_end = .; 35 } >SRAM 36 37 .text_sram : ALIGN(4096) { 38 __bl31_sram_text_start = .; 39 *(.sram.text) 40 *(.sram.rodata) 41 . = ALIGN(4096); 42 __bl31_sram_text_end = .; 43 } >SRAM 44 45 .data_sram : ALIGN(4096) { 46 __bl31_sram_data_start = .; 47 *(.sram.data) 48 . = ALIGN(4096); 49 __bl31_sram_data_end = .; 50 } >SRAM 51 52 .stack_sram : ALIGN(4096) { 53 __bl31_sram_stack_start = .; 54 . += 4096; 55 __bl31_sram_stack_end = .; 56 } >SRAM 57 58 . = PMUSRAM_BASE; 59 60 /* 61 * pmu_cpuson_entrypoint request address 62 * align 64K when resume, so put it in the 63 * start of pmusram 64 */ 65 .pmusram : { 66 ASSERT(. == ALIGN(64 * 1024), 67 ".pmusram.entry request 64K aligned."); 68 *(.pmusram.entry) 69 __bl31_pmusram_text_start = .; 70 *(.pmusram.text) 71 *(.pmusram.rodata) 72 __bl31_pmusram_text_end = .; 73 __bl31_pmusram_data_start = .; 74 *(.pmusram.data) 75 __bl31_pmusram_data_end = .; 76 77 } >PMUSRAM 78} 79 80#endif /* __ROCKCHIP_PLAT_LD_S__ */ 81