1ec693569SCaesar Wang/* 2ec693569SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3ec693569SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5ec693569SCaesar Wang */ 6ec693569SCaesar Wang#ifndef __ROCKCHIP_PLAT_LD_S__ 7ec693569SCaesar Wang#define __ROCKCHIP_PLAT_LD_S__ 8ec693569SCaesar Wang 9ec693569SCaesar WangMEMORY { 10ec693569SCaesar Wang SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 11*bc5c3007SLin Huang PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 12ec693569SCaesar Wang} 13ec693569SCaesar Wang 14ec693569SCaesar WangSECTIONS 15ec693569SCaesar Wang{ 16ec693569SCaesar Wang . = SRAM_BASE; 17ec693569SCaesar Wang ASSERT(. == ALIGN(4096), 18ec693569SCaesar Wang "SRAM_BASE address is not aligned on a page boundary.") 19ec693569SCaesar Wang 20ec693569SCaesar Wang /* 21ec693569SCaesar Wang * The SRAM space allocation for RK3399 22ec693569SCaesar Wang * ---------------- 238382e17cSCaesar Wang * | m0 code bin 248382e17cSCaesar Wang * ---------------- 25ec693569SCaesar Wang * | sram text 26ec693569SCaesar Wang * ---------------- 27ec693569SCaesar Wang * | sram data 28ec693569SCaesar Wang * ---------------- 29ec693569SCaesar Wang */ 308382e17cSCaesar Wang .incbin_sram : ALIGN(4096) { 318382e17cSCaesar Wang __sram_incbin_start = .; 328382e17cSCaesar Wang *(.sram.incbin) 338382e17cSCaesar Wang . = ALIGN(4096); 348382e17cSCaesar Wang __sram_incbin_end = .; 358382e17cSCaesar Wang } >SRAM 368382e17cSCaesar Wang 37ec693569SCaesar Wang .text_sram : ALIGN(4096) { 38ec693569SCaesar Wang __bl31_sram_text_start = .; 39ec693569SCaesar Wang *(.sram.text) 40ec693569SCaesar Wang *(.sram.rodata) 41ec693569SCaesar Wang . = ALIGN(4096); 42ec693569SCaesar Wang __bl31_sram_text_end = .; 43ec693569SCaesar Wang } >SRAM 44ec693569SCaesar Wang 45ec693569SCaesar Wang .data_sram : ALIGN(4096) { 46ec693569SCaesar Wang __bl31_sram_data_start = .; 47ec693569SCaesar Wang *(.sram.data) 48ec693569SCaesar Wang . = ALIGN(4096); 49ec693569SCaesar Wang __bl31_sram_data_end = .; 50ec693569SCaesar Wang } >SRAM 51*bc5c3007SLin Huang 52*bc5c3007SLin Huang .stack_sram : ALIGN(4096) { 53*bc5c3007SLin Huang __bl31_sram_stack_start = .; 54*bc5c3007SLin Huang . += 4096; 55*bc5c3007SLin Huang __bl31_sram_stack_end = .; 56*bc5c3007SLin Huang } >SRAM 57*bc5c3007SLin Huang 58*bc5c3007SLin Huang . = PMUSRAM_BASE; 59*bc5c3007SLin Huang 60*bc5c3007SLin Huang /* 61*bc5c3007SLin Huang * pmu_cpuson_entrypoint request address 62*bc5c3007SLin Huang * align 64K when resume, so put it in the 63*bc5c3007SLin Huang * start of pmusram 64*bc5c3007SLin Huang */ 65*bc5c3007SLin Huang .pmusram : { 66*bc5c3007SLin Huang ASSERT(. == ALIGN(64 * 1024), 67*bc5c3007SLin Huang ".pmusram.entry request 64K aligned."); 68*bc5c3007SLin Huang *(.pmusram.entry) 69*bc5c3007SLin Huang __bl31_pmusram_text_start = .; 70*bc5c3007SLin Huang *(.pmusram.text) 71*bc5c3007SLin Huang *(.pmusram.rodata) 72*bc5c3007SLin Huang __bl31_pmusram_text_end = .; 73*bc5c3007SLin Huang __bl31_pmusram_data_start = .; 74*bc5c3007SLin Huang *(.pmusram.data) 75*bc5c3007SLin Huang __bl31_pmusram_data_end = .; 76*bc5c3007SLin Huang 77*bc5c3007SLin Huang } >PMUSRAM 78ec693569SCaesar Wang} 79ec693569SCaesar Wang 80ec693569SCaesar Wang#endif /* __ROCKCHIP_PLAT_LD_S__ */ 81