1ec693569SCaesar Wang/* 2ec693569SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3ec693569SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5ec693569SCaesar Wang */ 6ec693569SCaesar Wang#ifndef __ROCKCHIP_PLAT_LD_S__ 7ec693569SCaesar Wang#define __ROCKCHIP_PLAT_LD_S__ 8ec693569SCaesar Wang 9*a2aedac2SAntonio Nino Diaz#include <xlat_tables_defs.h> 10*a2aedac2SAntonio Nino Diaz 11ec693569SCaesar WangMEMORY { 12ec693569SCaesar Wang SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 13bc5c3007SLin Huang PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 14ec693569SCaesar Wang} 15ec693569SCaesar Wang 16ec693569SCaesar WangSECTIONS 17ec693569SCaesar Wang{ 18ec693569SCaesar Wang . = SRAM_BASE; 19*a2aedac2SAntonio Nino Diaz ASSERT(. == ALIGN(PAGE_SIZE), 20ec693569SCaesar Wang "SRAM_BASE address is not aligned on a page boundary.") 21ec693569SCaesar Wang 22ec693569SCaesar Wang /* 23ec693569SCaesar Wang * The SRAM space allocation for RK3399 24ec693569SCaesar Wang * ---------------- 258382e17cSCaesar Wang * | m0 code bin 268382e17cSCaesar Wang * ---------------- 27ec693569SCaesar Wang * | sram text 28ec693569SCaesar Wang * ---------------- 29ec693569SCaesar Wang * | sram data 30ec693569SCaesar Wang * ---------------- 31ec693569SCaesar Wang */ 32*a2aedac2SAntonio Nino Diaz .incbin_sram : ALIGN(PAGE_SIZE) { 338382e17cSCaesar Wang __sram_incbin_start = .; 348382e17cSCaesar Wang *(.sram.incbin) 354e836d35SLin Huang __sram_incbin_real_end = .; 36*a2aedac2SAntonio Nino Diaz . = ALIGN(PAGE_SIZE); 378382e17cSCaesar Wang __sram_incbin_end = .; 388382e17cSCaesar Wang } >SRAM 394e836d35SLin Huang ASSERT((__sram_incbin_real_end - __sram_incbin_start) <= 404e836d35SLin Huang SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit") 418382e17cSCaesar Wang 42*a2aedac2SAntonio Nino Diaz .text_sram : ALIGN(PAGE_SIZE) { 43ec693569SCaesar Wang __bl31_sram_text_start = .; 44ec693569SCaesar Wang *(.sram.text) 45ec693569SCaesar Wang *(.sram.rodata) 464e836d35SLin Huang __bl31_sram_text_real_end = .; 47*a2aedac2SAntonio Nino Diaz . = ALIGN(PAGE_SIZE); 48ec693569SCaesar Wang __bl31_sram_text_end = .; 49ec693569SCaesar Wang } >SRAM 504e836d35SLin Huang ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <= 514e836d35SLin Huang SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit") 52ec693569SCaesar Wang 53*a2aedac2SAntonio Nino Diaz .data_sram : ALIGN(PAGE_SIZE) { 54ec693569SCaesar Wang __bl31_sram_data_start = .; 55ec693569SCaesar Wang *(.sram.data) 564e836d35SLin Huang __bl31_sram_data_real_end = .; 57*a2aedac2SAntonio Nino Diaz . = ALIGN(PAGE_SIZE); 58ec693569SCaesar Wang __bl31_sram_data_end = .; 59ec693569SCaesar Wang } >SRAM 604e836d35SLin Huang ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <= 614e836d35SLin Huang SRAM_DATA_LIMIT, ".data_sram has exceeded its limit") 62bc5c3007SLin Huang 63*a2aedac2SAntonio Nino Diaz .stack_sram : ALIGN(PAGE_SIZE) { 64bc5c3007SLin Huang __bl31_sram_stack_start = .; 65*a2aedac2SAntonio Nino Diaz . += PAGE_SIZE; 66bc5c3007SLin Huang __bl31_sram_stack_end = .; 67bc5c3007SLin Huang } >SRAM 68bc5c3007SLin Huang 69bc5c3007SLin Huang . = PMUSRAM_BASE; 70bc5c3007SLin Huang 71bc5c3007SLin Huang /* 72bc5c3007SLin Huang * pmu_cpuson_entrypoint request address 73bc5c3007SLin Huang * align 64K when resume, so put it in the 74bc5c3007SLin Huang * start of pmusram 75bc5c3007SLin Huang */ 76bc5c3007SLin Huang .pmusram : { 77bc5c3007SLin Huang ASSERT(. == ALIGN(64 * 1024), 78bc5c3007SLin Huang ".pmusram.entry request 64K aligned."); 79bc5c3007SLin Huang *(.pmusram.entry) 80bc5c3007SLin Huang __bl31_pmusram_text_start = .; 81bc5c3007SLin Huang *(.pmusram.text) 82bc5c3007SLin Huang *(.pmusram.rodata) 83bc5c3007SLin Huang __bl31_pmusram_text_end = .; 84bc5c3007SLin Huang __bl31_pmusram_data_start = .; 85bc5c3007SLin Huang *(.pmusram.data) 86bc5c3007SLin Huang __bl31_pmusram_data_end = .; 87bc5c3007SLin Huang 88bc5c3007SLin Huang } >PMUSRAM 89ec693569SCaesar Wang} 90ec693569SCaesar Wang 91ec693569SCaesar Wang#endif /* __ROCKCHIP_PLAT_LD_S__ */ 92