xref: /rk3399_ARM-atf/plat/rockchip/rk3399/include/plat.ld.S (revision 82cb2c1ad9897473743f08437d0a3995bed561b9)
1ec693569SCaesar Wang/*
2ec693569SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3ec693569SCaesar Wang *
4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause
5ec693569SCaesar Wang */
6ec693569SCaesar Wang#ifndef __ROCKCHIP_PLAT_LD_S__
7ec693569SCaesar Wang#define __ROCKCHIP_PLAT_LD_S__
8ec693569SCaesar Wang
9ec693569SCaesar WangMEMORY {
10ec693569SCaesar Wang    SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
11ec693569SCaesar Wang}
12ec693569SCaesar Wang
13ec693569SCaesar WangSECTIONS
14ec693569SCaesar Wang{
15ec693569SCaesar Wang	. = SRAM_BASE;
16ec693569SCaesar Wang	ASSERT(. == ALIGN(4096),
17ec693569SCaesar Wang		"SRAM_BASE address is not aligned on a page boundary.")
18ec693569SCaesar Wang
19ec693569SCaesar Wang	/*
20ec693569SCaesar Wang	 * The SRAM space allocation for RK3399
21ec693569SCaesar Wang	 * ----------------
228382e17cSCaesar Wang	 * | m0 code bin
238382e17cSCaesar Wang	 * ----------------
24ec693569SCaesar Wang	 * | sram text
25ec693569SCaesar Wang	 * ----------------
26ec693569SCaesar Wang	 * | sram data
27ec693569SCaesar Wang	 * ----------------
28ec693569SCaesar Wang	 */
298382e17cSCaesar Wang	.incbin_sram : ALIGN(4096) {
308382e17cSCaesar Wang		__sram_incbin_start = .;
318382e17cSCaesar Wang		*(.sram.incbin)
328382e17cSCaesar Wang		. = ALIGN(4096);
338382e17cSCaesar Wang		__sram_incbin_end = .;
348382e17cSCaesar Wang	} >SRAM
358382e17cSCaesar Wang
36ec693569SCaesar Wang	.text_sram : ALIGN(4096) {
37ec693569SCaesar Wang		__bl31_sram_text_start = .;
38ec693569SCaesar Wang		*(.sram.text)
39ec693569SCaesar Wang		*(.sram.rodata)
40ec693569SCaesar Wang		. = ALIGN(4096);
41ec693569SCaesar Wang		__bl31_sram_text_end = .;
42ec693569SCaesar Wang	} >SRAM
43ec693569SCaesar Wang
44ec693569SCaesar Wang	.data_sram : ALIGN(4096) {
45ec693569SCaesar Wang		__bl31_sram_data_start = .;
46ec693569SCaesar Wang		*(.sram.data)
47ec693569SCaesar Wang		. = ALIGN(4096);
48ec693569SCaesar Wang		__bl31_sram_data_end = .;
49ec693569SCaesar Wang	} >SRAM
50ec693569SCaesar Wang}
51ec693569SCaesar Wang
52ec693569SCaesar Wang#endif /* __ROCKCHIP_PLAT_LD_S__ */
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