1ec693569SCaesar Wang/* 2ec693569SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3ec693569SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5ec693569SCaesar Wang */ 6ec693569SCaesar Wang#ifndef __ROCKCHIP_PLAT_LD_S__ 7ec693569SCaesar Wang#define __ROCKCHIP_PLAT_LD_S__ 8ec693569SCaesar Wang 9ec693569SCaesar WangMEMORY { 10ec693569SCaesar Wang SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 11bc5c3007SLin Huang PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 12ec693569SCaesar Wang} 13ec693569SCaesar Wang 14ec693569SCaesar WangSECTIONS 15ec693569SCaesar Wang{ 16ec693569SCaesar Wang . = SRAM_BASE; 17ec693569SCaesar Wang ASSERT(. == ALIGN(4096), 18ec693569SCaesar Wang "SRAM_BASE address is not aligned on a page boundary.") 19ec693569SCaesar Wang 20ec693569SCaesar Wang /* 21ec693569SCaesar Wang * The SRAM space allocation for RK3399 22ec693569SCaesar Wang * ---------------- 238382e17cSCaesar Wang * | m0 code bin 248382e17cSCaesar Wang * ---------------- 25ec693569SCaesar Wang * | sram text 26ec693569SCaesar Wang * ---------------- 27ec693569SCaesar Wang * | sram data 28ec693569SCaesar Wang * ---------------- 29ec693569SCaesar Wang */ 308382e17cSCaesar Wang .incbin_sram : ALIGN(4096) { 318382e17cSCaesar Wang __sram_incbin_start = .; 328382e17cSCaesar Wang *(.sram.incbin) 33*4e836d35SLin Huang __sram_incbin_real_end = .; 348382e17cSCaesar Wang . = ALIGN(4096); 358382e17cSCaesar Wang __sram_incbin_end = .; 368382e17cSCaesar Wang } >SRAM 37*4e836d35SLin Huang ASSERT((__sram_incbin_real_end - __sram_incbin_start) <= 38*4e836d35SLin Huang SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit") 398382e17cSCaesar Wang 40ec693569SCaesar Wang .text_sram : ALIGN(4096) { 41ec693569SCaesar Wang __bl31_sram_text_start = .; 42ec693569SCaesar Wang *(.sram.text) 43ec693569SCaesar Wang *(.sram.rodata) 44*4e836d35SLin Huang __bl31_sram_text_real_end = .; 45ec693569SCaesar Wang . = ALIGN(4096); 46ec693569SCaesar Wang __bl31_sram_text_end = .; 47ec693569SCaesar Wang } >SRAM 48*4e836d35SLin Huang ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <= 49*4e836d35SLin Huang SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit") 50ec693569SCaesar Wang 51ec693569SCaesar Wang .data_sram : ALIGN(4096) { 52ec693569SCaesar Wang __bl31_sram_data_start = .; 53ec693569SCaesar Wang *(.sram.data) 54*4e836d35SLin Huang __bl31_sram_data_real_end = .; 55ec693569SCaesar Wang . = ALIGN(4096); 56ec693569SCaesar Wang __bl31_sram_data_end = .; 57ec693569SCaesar Wang } >SRAM 58*4e836d35SLin Huang ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <= 59*4e836d35SLin Huang SRAM_DATA_LIMIT, ".data_sram has exceeded its limit") 60bc5c3007SLin Huang 61bc5c3007SLin Huang .stack_sram : ALIGN(4096) { 62bc5c3007SLin Huang __bl31_sram_stack_start = .; 63bc5c3007SLin Huang . += 4096; 64bc5c3007SLin Huang __bl31_sram_stack_end = .; 65bc5c3007SLin Huang } >SRAM 66bc5c3007SLin Huang 67bc5c3007SLin Huang . = PMUSRAM_BASE; 68bc5c3007SLin Huang 69bc5c3007SLin Huang /* 70bc5c3007SLin Huang * pmu_cpuson_entrypoint request address 71bc5c3007SLin Huang * align 64K when resume, so put it in the 72bc5c3007SLin Huang * start of pmusram 73bc5c3007SLin Huang */ 74bc5c3007SLin Huang .pmusram : { 75bc5c3007SLin Huang ASSERT(. == ALIGN(64 * 1024), 76bc5c3007SLin Huang ".pmusram.entry request 64K aligned."); 77bc5c3007SLin Huang *(.pmusram.entry) 78bc5c3007SLin Huang __bl31_pmusram_text_start = .; 79bc5c3007SLin Huang *(.pmusram.text) 80bc5c3007SLin Huang *(.pmusram.rodata) 81bc5c3007SLin Huang __bl31_pmusram_text_end = .; 82bc5c3007SLin Huang __bl31_pmusram_data_start = .; 83bc5c3007SLin Huang *(.pmusram.data) 84bc5c3007SLin Huang __bl31_pmusram_data_end = .; 85bc5c3007SLin Huang 86bc5c3007SLin Huang } >PMUSRAM 87ec693569SCaesar Wang} 88ec693569SCaesar Wang 89ec693569SCaesar Wang#endif /* __ROCKCHIP_PLAT_LD_S__ */ 90