1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON(n) ((n) * 4) 38 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 39 #define PLL_MODE_MSK 0x03 40 #define PLL_MODE_SHIFT 0x08 41 #define PLL_BYPASS_MSK 0x01 42 #define PLL_BYPASS_SHIFT 0x01 43 #define PLL_PWRDN_MSK 0x01 44 #define PLL_PWRDN_SHIFT 0x0 45 #define PLL_BYPASS BIT(1) 46 #define PLL_PWRDN BIT(0) 47 48 #define NO_PLL_BYPASS (0x00) 49 #define NO_PLL_PWRDN (0x00) 50 51 #define FBDIV(n) ((0xfff << 16) | n) 52 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 53 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 54 #define REFDIV(n) ((0x3F << 16) | n) 55 #define PLL_LOCK(n) ((n >> 31) & 0x1) 56 57 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 58 PLL_MODE_MSK, PLL_MODE_SHIFT) 59 60 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 61 PLL_MODE_MSK, PLL_MODE_SHIFT) 62 63 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 64 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 65 66 #define PLL_CON_COUNT 0x06 67 #define CRU_CLKSEL_COUNT 108 68 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) 69 70 #define PMUCRU_CLKSEL_CONUT 0x06 71 #define PMUCRU_CLKSEL_OFFSET 0x080 72 #define REG_SIZE 0x04 73 #define REG_SOC_WMSK 0xffff0000 74 #define CLK_GATE_MASK 0x01 75 76 #define SGRF_SOC_COUNT 0x17 77 #define PMUCRU_GATE_COUNT 0x03 78 #define CRU_GATE_COUNT 0x23 79 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 80 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 81 82 enum plls_id { 83 ALPLL_ID = 0, 84 ABPLL_ID, 85 DPLL_ID, 86 CPLL_ID, 87 GPLL_ID, 88 NPLL_ID, 89 VPLL_ID, 90 PPLL_ID, 91 END_PLL_ID, 92 }; 93 94 #define CLST_L_CPUS_MSK (0xf) 95 #define CLST_B_CPUS_MSK (0x3) 96 97 enum pll_work_mode { 98 SLOW_MODE = 0x00, 99 NORMAL_MODE = 0x01, 100 DEEP_SLOW_MODE = 0x02, 101 }; 102 103 enum glb_sft_reset { 104 PMU_RST_BY_FIRST_SFT, 105 PMU_RST_BY_SECOND_SFT = BIT(2), 106 PMU_RST_NOT_BY_SFT = BIT(3), 107 }; 108 109 struct deepsleep_data_s { 110 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 111 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 112 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 113 uint32_t cru_gate_con[CRU_GATE_COUNT]; 114 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 115 uint32_t sgrf_con[SGRF_SOC_COUNT]; 116 }; 117 118 /************************************************** 119 * pmugrf reg, offset 120 **************************************************/ 121 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 122 123 /************************************************** 124 * DCF reg, offset 125 **************************************************/ 126 #define DCF_DCF_CTRL 0x0 127 #define DCF_DCF_ADDR 0x8 128 #define DCF_DCF_ISR 0xc 129 #define DCF_DCF_TOSET 0x14 130 #define DCF_DCF_TOCMD 0x18 131 #define DCF_DCF_CMD_CFG 0x1c 132 133 /* DCF_DCF_ISR */ 134 #define DCF_TIMEOUT (1 << 2) 135 #define DCF_ERR (1 << 1) 136 #define DCF_DONE (1 << 0) 137 138 /* DCF_DCF_CTRL */ 139 #define DCF_VOP_HW_EN (1 << 2) 140 #define DCF_STOP (1 << 1) 141 #define DCF_START (1 << 0) 142 143 #define CYCL_24M_CNT_US(us) (24 * us) 144 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 145 #define CYCL_32K_CNT_MS(ms) (ms * 32) 146 147 /************************************************** 148 * secure timer 149 **************************************************/ 150 151 /* chanal0~5 */ 152 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 153 /* chanal6~11 */ 154 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 155 156 /* low 32 bits */ 157 #define TIMER_END_COUNT0 0x00 158 /* high 32 bits */ 159 #define TIMER_END_COUNT1 0x04 160 161 #define TIMER_CURRENT_VALUE0 0x08 162 #define TIMER_CURRENT_VALUE1 0x0C 163 164 /* low 32 bits */ 165 #define TIMER_INIT_COUNT0 0x10 166 /* high 32 bits */ 167 #define TIMER_INIT_COUNT1 0x14 168 169 #define TIMER_INTSTATUS 0x18 170 #define TIMER_CONTROL_REG 0x1c 171 172 #define TIMER_EN 0x1 173 174 #define TIMER_FMODE (0x0 << 1) 175 #define TIMER_RMODE (0x1 << 1) 176 177 /************************************************** 178 * secure WDT 179 **************************************************/ 180 #define WDT_CM0_EN 0x0 181 #define WDT_CM0_DIS 0x1 182 #define WDT_CA53_EN 0x0 183 #define WDT_CA53_DIS 0x1 184 185 #define PCLK_WDT_CA53_GATE_SHIFT 8 186 #define PCLK_WDT_CM0_GATE_SHIFT 10 187 188 #define WDT_CA53_1BIT_MASK 0x1 189 #define WDT_CM0_1BIT_MASK 0x1 190 191 /************************************************** 192 * cru reg, offset 193 **************************************************/ 194 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 195 196 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 197 /* reset release*/ 198 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 199 200 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 201 /* reset release*/ 202 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 203 204 #define CRU_GLB_RST_CON 0x0510 205 #define CRU_GLB_SRST_FST 0x0500 206 #define CRU_GLB_SRST_SND 0x0504 207 208 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 209 #define PCLK_GPIO2_GATE_SHIFT 3 210 #define PCLK_GPIO3_GATE_SHIFT 4 211 #define PCLK_GPIO4_GATE_SHIFT 5 212 213 /************************************************** 214 * pmu cru reg, offset 215 **************************************************/ 216 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 217 /* reset hold*/ 218 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 219 /* reset hold release*/ 220 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 221 222 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 223 #define CRU_PMU_WDTRST_EN 0x0 224 225 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 226 #define CRU_PMU_FIRST_SFTRST_EN 0x0 227 228 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 229 #define PCLK_GPIO0_GATE_SHIFT 3 230 #define PCLK_GPIO1_GATE_SHIFT 4 231 232 /************************************************** 233 * sgrf reg, offset 234 **************************************************/ 235 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 236 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 237 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 238 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 239 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 240 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 241 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 242 243 /* security config for master */ 244 #define SGRF_SOC_CON_WMSK 0xffff0000 245 /* All of master in ns */ 246 #define SGRF_SOC_ALLMST_NS 0xffff 247 248 /* security config for slave */ 249 #define SGRF_SLV_S_WMSK 0xffff0000 250 #define SGRF_SLV_S_ALL_NS 0x0 251 252 /* security config pmu slave ip */ 253 /* All of slaves is ns */ 254 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 255 /* slaves secure attr is configed */ 256 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 257 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 258 259 #define SGRF_PMUSRAM_S BIT(8) 260 261 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 262 SGRF_PMUSRAM_S) 263 /* ddr region */ 264 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ 265 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ 266 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 267 268 /* The MST access the ddr rgn n with secure attribution */ 269 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 270 /* bits[16:8]*/ 271 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 272 273 /* dmac to periph s or ns*/ 274 #define SGRF_DMAC_CFG_S 0xffff0000 275 276 #define DMAC1_RGN_NS 0xff000000 277 #define DMAC0_RGN_NS 0x00ff0000 278 279 #define DMAC0_BOOT_CFG_NS 0xfffffff8 280 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 281 #define DMAC0_BOOT_ADDR_NS 0xffff0000 282 283 #define DMAC1_BOOT_CFG_NS 0xffff0008 284 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 285 #define DMAC1_BOOT_ADDR_NS 0xffff0000 286 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 287 #define DMAC1_BOOT_IRQ_NS 0xffffffff 288 289 #define CPU_BOOT_ADDR_WMASK 0xffff0000 290 #define CPU_BOOT_ADDR_ALIGN 16 291 292 #define GRF_IOMUX_2BIT_MASK 0x3 293 #define GRF_IOMUX_GPIO 0x0 294 295 #define GRF_GPIO4C2_IOMUX_SHIFT 4 296 #define GRF_GPIO4C2_IOMUX_PWM 0x1 297 #define GRF_GPIO4C6_IOMUX_SHIFT 12 298 #define GRF_GPIO4C6_IOMUX_PWM 0x1 299 300 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 301 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 302 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 303 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 304 305 #define PWM_DISABLE (0 << 0) 306 #define PWM_ENABLE (1 << 0) 307 308 /* grf reg offset */ 309 #define GRF_DDRC0_CON0 0xe380 310 #define GRF_DDRC0_CON1 0xe384 311 #define GRF_DDRC1_CON0 0xe388 312 #define GRF_DDRC1_CON1 0xe38c 313 314 #define PMUCRU_CLKSEL_CON0 0x0080 315 #define PMUCRU_CLKGATE_CON2 0x0108 316 #define PMUCRU_SOFTRST_CON0 0x0110 317 #define PMUCRU_GATEDIS_CON0 0x0130 318 319 #define SGRF_SOC_CON6 0x0e018 320 #define SGRF_PERILP_CON0 0x08100 321 #define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4) 322 #define SGRF_PMU_CON0 0x0c100 323 #define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) 324 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) 325 326 /* 327 * When system reset in running state, we want the cpus to be reboot 328 * from maskrom (system reboot), 329 * the pmusgrf reset-hold bits needs to be released. 330 * When system wake up from system deep suspend, some soc will be reset 331 * when waked up, 332 * we want the bootcpu to be reboot from pmusram, 333 * the pmusgrf reset-hold bits needs to be held. 334 */ 335 static inline void pmu_sgrf_rst_hld_release(void) 336 { 337 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 338 CRU_PMU_SGRF_RST_RLS); 339 } 340 341 static inline void pmu_sgrf_rst_hld(void) 342 { 343 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 344 CRU_PMU_SGRF_RST_HOLD); 345 } 346 347 /* funciton*/ 348 void __dead2 soc_global_soft_reset(void); 349 void secure_watchdog_disable(); 350 void secure_watchdog_restore(); 351 void disable_dvfs_plls(void); 352 void disable_nodvfs_plls(void); 353 void enable_dvfs_plls(void); 354 void enable_nodvfs_plls(void); 355 void prepare_abpll_for_ddrctrl(void); 356 void restore_abpll(void); 357 void restore_dpll(void); 358 void clk_gate_con_save(void); 359 void clk_gate_con_disable(void); 360 void clk_gate_con_restore(void); 361 void sgrf_init(void); 362 #endif /* __SOC_H__ */ 363