1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON(n) ((n) * 4) 38 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 39 #define PLL_MODE_MSK 0x03 40 #define PLL_MODE_SHIFT 0x08 41 #define PLL_BYPASS_MSK 0x01 42 #define PLL_BYPASS_SHIFT 0x01 43 #define PLL_PWRDN_MSK 0x01 44 #define PLL_PWRDN_SHIFT 0x0 45 #define PLL_BYPASS BIT(1) 46 #define PLL_PWRDN BIT(0) 47 48 #define NO_PLL_BYPASS (0x00) 49 #define NO_PLL_PWRDN (0x00) 50 51 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 52 PLL_MODE_MSK, PLL_MODE_SHIFT) 53 54 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 55 PLL_MODE_MSK, PLL_MODE_SHIFT) 56 57 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 58 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 59 60 #define PLL_CON_COUNT 0x06 61 #define CRU_CLKSEL_COUNT 0x108 62 #define CRU_CLKSEL_CON(n) (0x80 + (n) * 4) 63 64 #define PMUCRU_CLKSEL_CONUT 0x06 65 #define PMUCRU_CLKSEL_OFFSET 0x080 66 #define REG_SIZE 0x04 67 #define REG_SOC_WMSK 0xffff0000 68 #define CLK_GATE_MASK 0x01 69 70 #define PMUCRU_GATE_COUNT 0x03 71 #define CRU_GATE_COUNT 0x23 72 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 73 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 74 75 enum plls_id { 76 ALPLL_ID = 0, 77 ABPLL_ID, 78 DPLL_ID, 79 CPLL_ID, 80 GPLL_ID, 81 NPLL_ID, 82 VPLL_ID, 83 PPLL_ID, 84 END_PLL_ID, 85 }; 86 87 #define CLST_L_CPUS_MSK (0xf) 88 #define CLST_B_CPUS_MSK (0x3) 89 90 enum pll_work_mode { 91 SLOW_MODE = 0x00, 92 NORMAL_MODE = 0x01, 93 DEEP_SLOW_MODE = 0x02, 94 }; 95 96 enum glb_sft_reset { 97 PMU_RST_BY_FIRST_SFT, 98 PMU_RST_BY_SECOND_SFT = BIT(2), 99 PMU_RST_NOT_BY_SFT = BIT(3), 100 }; 101 102 struct deepsleep_data_s { 103 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 104 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 105 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 106 uint32_t cru_gate_con[CRU_GATE_COUNT]; 107 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 108 }; 109 110 #define CYCL_24M_CNT_US(us) (24 * us) 111 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 112 #define CYCL_32K_CNT_MS(ms) (ms * 32) 113 114 /************************************************** 115 * secure timer 116 **************************************************/ 117 118 /* chanal0~5 */ 119 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 120 /* chanal6~11 */ 121 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 122 123 /* low 32 bits */ 124 #define TIMER_END_COUNT0 0x00 125 /* high 32 bits */ 126 #define TIMER_END_COUNT1 0x04 127 128 #define TIMER_CURRENT_VALUE0 0x08 129 #define TIMER_CURRENT_VALUE1 0x0C 130 131 /* low 32 bits */ 132 #define TIMER_INIT_COUNT0 0x10 133 /* high 32 bits */ 134 #define TIMER_INIT_COUNT1 0x14 135 136 #define TIMER_INTSTATUS 0x18 137 #define TIMER_CONTROL_REG 0x1c 138 139 #define TIMER_EN 0x1 140 141 #define TIMER_FMODE (0x0 << 1) 142 #define TIMER_RMODE (0x1 << 1) 143 144 /************************************************** 145 * cru reg, offset 146 **************************************************/ 147 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 148 149 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 150 /* reset release*/ 151 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 152 153 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 154 /* reset release*/ 155 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 156 157 #define CRU_GLB_RST_CON 0x0510 158 #define CRU_GLB_SRST_FST 0x0500 159 #define CRU_GLB_SRST_SND 0x0504 160 161 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 162 #define PCLK_GPIO2_GATE_SHIFT 3 163 #define PCLK_GPIO3_GATE_SHIFT 4 164 #define PCLK_GPIO4_GATE_SHIFT 5 165 166 /************************************************** 167 * pmu cru reg, offset 168 **************************************************/ 169 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 170 /* reset hold*/ 171 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 172 /* reset hold release*/ 173 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 174 175 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 176 #define CRU_PMU_WDTRST_EN 0x0 177 178 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 179 #define CRU_PMU_FIRST_SFTRST_EN 0x0 180 181 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 182 #define PCLK_GPIO0_GATE_SHIFT 3 183 #define PCLK_GPIO1_GATE_SHIFT 4 184 185 /************************************************** 186 * sgrf reg, offset 187 **************************************************/ 188 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 189 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 190 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 191 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 192 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 193 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 194 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 195 196 /* security config for master */ 197 #define SGRF_SOC_CON_WMSK 0xffff0000 198 /* All of master in ns */ 199 #define SGRF_SOC_ALLMST_NS 0xffff 200 201 /* security config for slave */ 202 #define SGRF_SLV_S_WMSK 0xffff0000 203 #define SGRF_SLV_S_ALL_NS 0x0 204 205 /* security config pmu slave ip */ 206 /* All of slaves is ns */ 207 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 208 /* slaves secure attr is configed */ 209 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 210 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 211 212 #define SGRF_PMUSRAM_S BIT(8) 213 214 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 215 SGRF_PMUSRAM_S) 216 /* ddr region */ 217 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 218 219 /* The MST access the ddr rgn n with secure attribution */ 220 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 221 /* bits[16:8]*/ 222 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 223 224 /* dmac to periph s or ns*/ 225 #define SGRF_DMAC_CFG_S 0xffff0000 226 227 #define DMAC1_RGN_NS 0xff000000 228 #define DMAC0_RGN_NS 0x00ff0000 229 230 #define DMAC0_BOOT_CFG_NS 0xfffffff8 231 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 232 #define DMAC0_BOOT_ADDR_NS 0xffff0000 233 234 #define DMAC1_BOOT_CFG_NS 0xffff0008 235 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 236 #define DMAC1_BOOT_ADDR_NS 0xffff0000 237 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 238 #define DMAC1_BOOT_IRQ_NS 0xffffffff 239 240 #define CPU_BOOT_ADDR_WMASK 0xffff0000 241 #define CPU_BOOT_ADDR_ALIGN 16 242 243 /* 244 * When system reset in running state, we want the cpus to be reboot 245 * from maskrom (system reboot), 246 * the pmusgrf reset-hold bits needs to be released. 247 * When system wake up from system deep suspend, some soc will be reset 248 * when waked up, 249 * we want the bootcpu to be reboot from pmusram, 250 * the pmusgrf reset-hold bits needs to be held. 251 */ 252 static inline void pmu_sgrf_rst_hld_release(void) 253 { 254 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 255 CRU_PMU_SGRF_RST_RLS); 256 } 257 258 static inline void pmu_sgrf_rst_hld(void) 259 { 260 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 261 CRU_PMU_SGRF_RST_HOLD); 262 } 263 264 /* funciton*/ 265 void __dead2 soc_global_soft_reset(void); 266 void plls_resume(void); 267 void plls_suspend(void); 268 void clk_gate_con_save(void); 269 void clk_gate_con_disable(void); 270 void clk_gate_con_restore(void); 271 #endif /* __SOC_H__ */ 272