1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON_OFFSET 0x000 38 #define PMUCRU_PPLL_CON_BASE_ADDR (PMUCRU_BASE + PMUCRU_PPLL_CON_OFFSET) 39 #define PMUCRU_PPLL_CON_CONUT 0x06 40 41 #define PMUCRU_PPLL_CON(num) (PMUCRU_PPLL_CON_BASE_ADDR + num * 4) 42 #define CRU_PLL_CON(pll_id, num) (CRU_BASE + pll_id * 0x20 + num * 4) 43 #define PLL_MODE_MSK 0x03 44 #define PLL_MODE_SHIFT 0x08 45 #define PLL_BYPASS_MSK 0x01 46 #define PLL_BYPASS_SHIFT 0x01 47 #define PLL_PWRDN_MSK 0x01 48 #define PLL_PWRDN_SHIFT 0x0 49 #define PLL_BYPASS BIT(1) 50 #define PLL_PWRDN BIT(0) 51 52 #define NO_PLL_BYPASS (0x00) 53 #define NO_PLL_PWRDN (0x00) 54 55 #define PLL_SLOW_MODE BITS_WITH_WMASK(PLL_MODE_MSK,\ 56 SLOW_MODE, PLL_MODE_SHIFT) 57 #define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS_MSK,\ 58 PLL_BYPASS, PLL_BYPASS_SHIFT) 59 #define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS_MSK,\ 60 NO_PLL_BYPASS, PLL_BYPASS_SHIFT) 61 #define PLL_NOMAL_MODE BITS_WITH_WMASK(PLL_MODE_MSK,\ 62 NORMAL_MODE, PLL_MODE_SHIFT) 63 64 #define PLL_CON_COUNT 0x06 65 #define CRU_CLKSEL_COUNT 0x108 66 #define CRU_CLKSEL_OFFSET 0x300 67 68 #define PMUCRU_CLKSEL_CONUT 0x06 69 #define PMUCRU_CLKSEL_OFFSET 0x080 70 #define REG_SIZE 0x04 71 #define REG_SOC_WMSK 0xffff0000 72 73 enum plls_id { 74 ALPLL_ID = 0, 75 ABPLL_ID, 76 DPLL_ID, 77 CPLL_ID, 78 GPLL_ID, 79 NPLL_ID, 80 VPLL_ID, 81 PPLL_ID, 82 END_PLL_ID, 83 }; 84 85 enum pll_work_mode { 86 SLOW_MODE = 0x00, 87 NORMAL_MODE = 0x01, 88 DEEP_SLOW_MODE = 0x02, 89 }; 90 91 enum glb_sft_reset { 92 PMU_RST_BY_FIRST_SFT, 93 PMU_RST_BY_SECOND_SFT = BIT(2), 94 PMU_RST_NOT_BY_SFT = BIT(3), 95 }; 96 97 struct deepsleep_data_s { 98 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 99 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 100 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 101 }; 102 103 /************************************************** 104 * secure timer 105 **************************************************/ 106 107 /* chanal0~5 */ 108 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 109 /* chanal6~11 */ 110 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 111 112 /* low 32 bits */ 113 #define TIMER_END_COUNT0 0x00 114 /* high 32 bits */ 115 #define TIMER_END_COUNT1 0x04 116 117 #define TIMER_CURRENT_VALUE0 0x08 118 #define TIMER_CURRENT_VALUE1 0x0C 119 120 /* low 32 bits */ 121 #define TIMER_INIT_COUNT0 0x10 122 /* high 32 bits */ 123 #define TIMER_INIT_COUNT1 0x14 124 125 #define TIMER_INTSTATUS 0x18 126 #define TIMER_CONTROL_REG 0x1c 127 128 #define TIMER_EN 0x1 129 130 #define TIMER_FMODE (0x0 << 1) 131 #define TIMER_RMODE (0x1 << 1) 132 133 /************************************************** 134 * cru reg, offset 135 **************************************************/ 136 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 137 138 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 139 /* reset release*/ 140 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 141 142 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 143 /* reset release*/ 144 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 145 146 #define CRU_GLB_RST_CON 0x0510 147 #define CRU_GLB_SRST_FST 0x0500 148 #define CRU_GLB_SRST_SND 0x0504 149 150 /************************************************** 151 * pmu cru reg, offset 152 **************************************************/ 153 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 154 /* reset hold*/ 155 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 156 /* reset hold release*/ 157 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 158 /************************************************** 159 * sgrf reg, offset 160 **************************************************/ 161 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 162 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 163 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 164 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 165 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 166 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 167 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 168 169 /* security config for master */ 170 #define SGRF_SOC_CON_WMSK 0xffff0000 171 /* All of master in ns */ 172 #define SGRF_SOC_ALLMST_NS 0xffff 173 174 /* security config for slave */ 175 #define SGRF_SLV_S_WMSK 0xffff0000 176 #define SGRF_SLV_S_ALL_NS 0x0 177 178 /* security config pmu slave ip */ 179 /* All of slaves is ns */ 180 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 181 /* slaves secure attr is configed */ 182 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 183 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 184 185 #define SGRF_PMUSRAM_S BIT(8) 186 187 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 188 SGRF_PMUSRAM_S) 189 /* ddr region */ 190 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 191 192 /* The MST access the ddr rgn n with secure attribution */ 193 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 194 /* bits[16:8]*/ 195 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 196 197 /* dmac to periph s or ns*/ 198 #define SGRF_DMAC_CFG_S 0xffff0000 199 200 #define DMAC1_RGN_NS 0xff000000 201 #define DMAC0_RGN_NS 0x00ff0000 202 203 #define DMAC0_BOOT_CFG_NS 0xfffffff8 204 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 205 #define DMAC0_BOOT_ADDR_NS 0xffff0000 206 207 #define DMAC1_BOOT_CFG_NS 0xffff0008 208 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 209 #define DMAC1_BOOT_ADDR_NS 0xffff0000 210 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 211 #define DMAC1_BOOT_IRQ_NS 0xffffffff 212 213 #define CPU_BOOT_ADDR_WMASK 0xffff0000 214 #define CPU_BOOT_ADDR_ALIGN 16 215 216 /* 217 * When system reset in running state, we want the cpus to be reboot 218 * from maskrom (system reboot), 219 * the pmusgrf reset-hold bits needs to be released. 220 * When system wake up from system deep suspend, some soc will be reset 221 * when waked up, 222 * we want the bootcpu to be reboot from pmusram, 223 * the pmusgrf reset-hold bits needs to be held. 224 */ 225 static inline void pmu_sgrf_rst_hld_release(void) 226 { 227 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 228 CRU_PMU_SGRF_RST_RLS); 229 } 230 231 static inline void pmu_sgrf_rst_hld(void) 232 { 233 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 234 CRU_PMU_SGRF_RST_HOLD); 235 } 236 237 /* funciton*/ 238 void __dead2 soc_global_soft_reset(void); 239 void plls_resume(void); 240 void plls_suspend(void); 241 242 #endif /* __SOC_H__ */ 243