1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON_OFFSET 0x000 38 #define PMUCRU_PPLL_CON_BASE_ADDR (PMUCRU_BASE + PMUCRU_PPLL_CON_OFFSET) 39 #define PMUCRU_PPLL_CON_CONUT 0x06 40 41 #define PMUCRU_PPLL_CON(num) (PMUCRU_PPLL_CON_BASE_ADDR + num * 4) 42 #define CRU_PLL_CON(pll_id, num) (CRU_BASE + pll_id * 0x20 + num * 4) 43 #define PLL_MODE_MSK 0x03 44 #define PLL_MODE_SHIFT 0x08 45 #define PLL_BYPASS_MSK 0x01 46 #define PLL_BYPASS_SHIFT 0x01 47 #define PLL_PWRDN_MSK 0x01 48 #define PLL_PWRDN_SHIFT 0x0 49 #define PLL_BYPASS BIT(1) 50 #define PLL_PWRDN BIT(0) 51 52 #define NO_PLL_BYPASS (0x00) 53 #define NO_PLL_PWRDN (0x00) 54 55 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 56 PLL_MODE_MSK, PLL_MODE_SHIFT) 57 #define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS,\ 58 PLL_BYPASS_MSK,\ 59 PLL_BYPASS_SHIFT) 60 #define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(NO_PLL_BYPASS,\ 61 PLL_BYPASS_MSK,\ 62 PLL_BYPASS_SHIFT) 63 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 64 PLL_MODE_MSK, PLL_MODE_SHIFT) 65 66 #define PLL_CON_COUNT 0x06 67 #define CRU_CLKSEL_COUNT 0x108 68 #define CRU_CLKSEL_OFFSET 0x300 69 70 #define PMUCRU_CLKSEL_CONUT 0x06 71 #define PMUCRU_CLKSEL_OFFSET 0x080 72 #define REG_SIZE 0x04 73 #define REG_SOC_WMSK 0xffff0000 74 75 enum plls_id { 76 ALPLL_ID = 0, 77 ABPLL_ID, 78 DPLL_ID, 79 CPLL_ID, 80 GPLL_ID, 81 NPLL_ID, 82 VPLL_ID, 83 PPLL_ID, 84 END_PLL_ID, 85 }; 86 87 enum pll_work_mode { 88 SLOW_MODE = 0x00, 89 NORMAL_MODE = 0x01, 90 DEEP_SLOW_MODE = 0x02, 91 }; 92 93 enum glb_sft_reset { 94 PMU_RST_BY_FIRST_SFT, 95 PMU_RST_BY_SECOND_SFT = BIT(2), 96 PMU_RST_NOT_BY_SFT = BIT(3), 97 }; 98 99 struct deepsleep_data_s { 100 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 101 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 102 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 103 }; 104 105 #define CYCL_24M_CNT_US(us) (24 * us) 106 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 107 108 /************************************************** 109 * secure timer 110 **************************************************/ 111 112 /* chanal0~5 */ 113 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 114 /* chanal6~11 */ 115 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 116 117 /* low 32 bits */ 118 #define TIMER_END_COUNT0 0x00 119 /* high 32 bits */ 120 #define TIMER_END_COUNT1 0x04 121 122 #define TIMER_CURRENT_VALUE0 0x08 123 #define TIMER_CURRENT_VALUE1 0x0C 124 125 /* low 32 bits */ 126 #define TIMER_INIT_COUNT0 0x10 127 /* high 32 bits */ 128 #define TIMER_INIT_COUNT1 0x14 129 130 #define TIMER_INTSTATUS 0x18 131 #define TIMER_CONTROL_REG 0x1c 132 133 #define TIMER_EN 0x1 134 135 #define TIMER_FMODE (0x0 << 1) 136 #define TIMER_RMODE (0x1 << 1) 137 138 /************************************************** 139 * cru reg, offset 140 **************************************************/ 141 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 142 143 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 144 /* reset release*/ 145 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 146 147 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 148 /* reset release*/ 149 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 150 151 #define CRU_GLB_RST_CON 0x0510 152 #define CRU_GLB_SRST_FST 0x0500 153 #define CRU_GLB_SRST_SND 0x0504 154 155 /************************************************** 156 * pmu cru reg, offset 157 **************************************************/ 158 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 159 /* reset hold*/ 160 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 161 /* reset hold release*/ 162 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 163 164 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 165 #define CRU_PMU_WDTRST_EN 0x0 166 167 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 168 #define CRU_PMU_FIRST_SFTRST_EN 0x0 169 170 /************************************************** 171 * sgrf reg, offset 172 **************************************************/ 173 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 174 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 175 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 176 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 177 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 178 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 179 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 180 181 /* security config for master */ 182 #define SGRF_SOC_CON_WMSK 0xffff0000 183 /* All of master in ns */ 184 #define SGRF_SOC_ALLMST_NS 0xffff 185 186 /* security config for slave */ 187 #define SGRF_SLV_S_WMSK 0xffff0000 188 #define SGRF_SLV_S_ALL_NS 0x0 189 190 /* security config pmu slave ip */ 191 /* All of slaves is ns */ 192 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 193 /* slaves secure attr is configed */ 194 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 195 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 196 197 #define SGRF_PMUSRAM_S BIT(8) 198 199 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 200 SGRF_PMUSRAM_S) 201 /* ddr region */ 202 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 203 204 /* The MST access the ddr rgn n with secure attribution */ 205 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 206 /* bits[16:8]*/ 207 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 208 209 /* dmac to periph s or ns*/ 210 #define SGRF_DMAC_CFG_S 0xffff0000 211 212 #define DMAC1_RGN_NS 0xff000000 213 #define DMAC0_RGN_NS 0x00ff0000 214 215 #define DMAC0_BOOT_CFG_NS 0xfffffff8 216 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 217 #define DMAC0_BOOT_ADDR_NS 0xffff0000 218 219 #define DMAC1_BOOT_CFG_NS 0xffff0008 220 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 221 #define DMAC1_BOOT_ADDR_NS 0xffff0000 222 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 223 #define DMAC1_BOOT_IRQ_NS 0xffffffff 224 225 #define CPU_BOOT_ADDR_WMASK 0xffff0000 226 #define CPU_BOOT_ADDR_ALIGN 16 227 228 /* 229 * When system reset in running state, we want the cpus to be reboot 230 * from maskrom (system reboot), 231 * the pmusgrf reset-hold bits needs to be released. 232 * When system wake up from system deep suspend, some soc will be reset 233 * when waked up, 234 * we want the bootcpu to be reboot from pmusram, 235 * the pmusgrf reset-hold bits needs to be held. 236 */ 237 static inline void pmu_sgrf_rst_hld_release(void) 238 { 239 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 240 CRU_PMU_SGRF_RST_RLS); 241 } 242 243 static inline void pmu_sgrf_rst_hld(void) 244 { 245 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 246 CRU_PMU_SGRF_RST_HOLD); 247 } 248 249 /* funciton*/ 250 void __dead2 soc_global_soft_reset(void); 251 void plls_resume(void); 252 void plls_suspend(void); 253 254 #endif /* __SOC_H__ */ 255