1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON_OFFSET 0x000 38 #define PMUCRU_PPLL_CON_BASE_ADDR (PMUCRU_BASE + PMUCRU_PPLL_CON_OFFSET) 39 #define PMUCRU_PPLL_CON_CONUT 0x06 40 41 #define PMUCRU_PPLL_CON(num) (PMUCRU_PPLL_CON_BASE_ADDR + num * 4) 42 #define CRU_PLL_CON(pll_id, num) (CRU_BASE + pll_id * 0x20 + num * 4) 43 #define PLL_MODE_MSK 0x03 44 #define PLL_MODE_SHIFT 0x08 45 #define PLL_BYPASS_MSK 0x01 46 #define PLL_BYPASS_SHIFT 0x01 47 #define PLL_PWRDN_MSK 0x01 48 #define PLL_PWRDN_SHIFT 0x0 49 #define PLL_BYPASS BIT(1) 50 #define PLL_PWRDN BIT(0) 51 52 #define NO_PLL_BYPASS (0x00) 53 #define NO_PLL_PWRDN (0x00) 54 55 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 56 PLL_MODE_MSK, PLL_MODE_SHIFT) 57 #define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS,\ 58 PLL_BYPASS_MSK,\ 59 PLL_BYPASS_SHIFT) 60 #define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(NO_PLL_BYPASS,\ 61 PLL_BYPASS_MSK,\ 62 PLL_BYPASS_SHIFT) 63 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 64 PLL_MODE_MSK, PLL_MODE_SHIFT) 65 66 #define PLL_CON_COUNT 0x06 67 #define CRU_CLKSEL_COUNT 0x108 68 #define CRU_CLKSEL_OFFSET 0x300 69 70 #define PMUCRU_CLKSEL_CONUT 0x06 71 #define PMUCRU_CLKSEL_OFFSET 0x080 72 #define REG_SIZE 0x04 73 #define REG_SOC_WMSK 0xffff0000 74 75 #define CLK_GATE_MASK 0x01 76 77 enum plls_id { 78 ALPLL_ID = 0, 79 ABPLL_ID, 80 DPLL_ID, 81 CPLL_ID, 82 GPLL_ID, 83 NPLL_ID, 84 VPLL_ID, 85 PPLL_ID, 86 END_PLL_ID, 87 }; 88 89 enum pll_work_mode { 90 SLOW_MODE = 0x00, 91 NORMAL_MODE = 0x01, 92 DEEP_SLOW_MODE = 0x02, 93 }; 94 95 enum glb_sft_reset { 96 PMU_RST_BY_FIRST_SFT, 97 PMU_RST_BY_SECOND_SFT = BIT(2), 98 PMU_RST_NOT_BY_SFT = BIT(3), 99 }; 100 101 struct deepsleep_data_s { 102 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 103 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 104 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 105 }; 106 107 #define CYCL_24M_CNT_US(us) (24 * us) 108 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 109 110 /************************************************** 111 * secure timer 112 **************************************************/ 113 114 /* chanal0~5 */ 115 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 116 /* chanal6~11 */ 117 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 118 119 /* low 32 bits */ 120 #define TIMER_END_COUNT0 0x00 121 /* high 32 bits */ 122 #define TIMER_END_COUNT1 0x04 123 124 #define TIMER_CURRENT_VALUE0 0x08 125 #define TIMER_CURRENT_VALUE1 0x0C 126 127 /* low 32 bits */ 128 #define TIMER_INIT_COUNT0 0x10 129 /* high 32 bits */ 130 #define TIMER_INIT_COUNT1 0x14 131 132 #define TIMER_INTSTATUS 0x18 133 #define TIMER_CONTROL_REG 0x1c 134 135 #define TIMER_EN 0x1 136 137 #define TIMER_FMODE (0x0 << 1) 138 #define TIMER_RMODE (0x1 << 1) 139 140 /************************************************** 141 * cru reg, offset 142 **************************************************/ 143 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 144 145 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 146 /* reset release*/ 147 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 148 149 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 150 /* reset release*/ 151 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 152 153 #define CRU_GLB_RST_CON 0x0510 154 #define CRU_GLB_SRST_FST 0x0500 155 #define CRU_GLB_SRST_SND 0x0504 156 157 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 158 #define PCLK_GPIO2_GATE_SHIFT 3 159 #define PCLK_GPIO3_GATE_SHIFT 4 160 #define PCLK_GPIO4_GATE_SHIFT 5 161 162 /************************************************** 163 * pmu cru reg, offset 164 **************************************************/ 165 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 166 /* reset hold*/ 167 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 168 /* reset hold release*/ 169 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 170 171 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 172 #define CRU_PMU_WDTRST_EN 0x0 173 174 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 175 #define CRU_PMU_FIRST_SFTRST_EN 0x0 176 177 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 178 #define PCLK_GPIO0_GATE_SHIFT 3 179 #define PCLK_GPIO1_GATE_SHIFT 4 180 181 /************************************************** 182 * sgrf reg, offset 183 **************************************************/ 184 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 185 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 186 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 187 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 188 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 189 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 190 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 191 192 /* security config for master */ 193 #define SGRF_SOC_CON_WMSK 0xffff0000 194 /* All of master in ns */ 195 #define SGRF_SOC_ALLMST_NS 0xffff 196 197 /* security config for slave */ 198 #define SGRF_SLV_S_WMSK 0xffff0000 199 #define SGRF_SLV_S_ALL_NS 0x0 200 201 /* security config pmu slave ip */ 202 /* All of slaves is ns */ 203 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 204 /* slaves secure attr is configed */ 205 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 206 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 207 208 #define SGRF_PMUSRAM_S BIT(8) 209 210 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 211 SGRF_PMUSRAM_S) 212 /* ddr region */ 213 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 214 215 /* The MST access the ddr rgn n with secure attribution */ 216 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 217 /* bits[16:8]*/ 218 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 219 220 /* dmac to periph s or ns*/ 221 #define SGRF_DMAC_CFG_S 0xffff0000 222 223 #define DMAC1_RGN_NS 0xff000000 224 #define DMAC0_RGN_NS 0x00ff0000 225 226 #define DMAC0_BOOT_CFG_NS 0xfffffff8 227 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 228 #define DMAC0_BOOT_ADDR_NS 0xffff0000 229 230 #define DMAC1_BOOT_CFG_NS 0xffff0008 231 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 232 #define DMAC1_BOOT_ADDR_NS 0xffff0000 233 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 234 #define DMAC1_BOOT_IRQ_NS 0xffffffff 235 236 #define CPU_BOOT_ADDR_WMASK 0xffff0000 237 #define CPU_BOOT_ADDR_ALIGN 16 238 239 /* 240 * When system reset in running state, we want the cpus to be reboot 241 * from maskrom (system reboot), 242 * the pmusgrf reset-hold bits needs to be released. 243 * When system wake up from system deep suspend, some soc will be reset 244 * when waked up, 245 * we want the bootcpu to be reboot from pmusram, 246 * the pmusgrf reset-hold bits needs to be held. 247 */ 248 static inline void pmu_sgrf_rst_hld_release(void) 249 { 250 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 251 CRU_PMU_SGRF_RST_RLS); 252 } 253 254 static inline void pmu_sgrf_rst_hld(void) 255 { 256 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 257 CRU_PMU_SGRF_RST_HOLD); 258 } 259 260 /* funciton*/ 261 void __dead2 soc_global_soft_reset(void); 262 void plls_resume(void); 263 void plls_suspend(void); 264 265 #endif /* __SOC_H__ */ 266