1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #include <utils.h> 35 36 #define GLB_SRST_FST_CFG_VAL 0xfdb9 37 #define GLB_SRST_SND_CFG_VAL 0xeca8 38 39 #define PMUCRU_PPLL_CON(n) ((n) * 4) 40 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 41 #define PLL_MODE_MSK 0x03 42 #define PLL_MODE_SHIFT 0x08 43 #define PLL_BYPASS_MSK 0x01 44 #define PLL_BYPASS_SHIFT 0x01 45 #define PLL_PWRDN_MSK 0x01 46 #define PLL_PWRDN_SHIFT 0x0 47 #define PLL_BYPASS BIT(1) 48 #define PLL_PWRDN BIT(0) 49 50 #define NO_PLL_BYPASS (0x00) 51 #define NO_PLL_PWRDN (0x00) 52 53 #define FBDIV(n) ((0xfff << 16) | n) 54 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 55 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 56 #define REFDIV(n) ((0x3F << 16) | n) 57 #define PLL_LOCK(n) ((n >> 31) & 0x1) 58 59 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 60 PLL_MODE_MSK, PLL_MODE_SHIFT) 61 62 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 63 PLL_MODE_MSK, PLL_MODE_SHIFT) 64 65 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 66 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 67 68 #define PLL_CON_COUNT 0x06 69 #define CRU_CLKSEL_COUNT 108 70 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) 71 72 #define PMUCRU_CLKSEL_CONUT 0x06 73 #define PMUCRU_CLKSEL_OFFSET 0x080 74 #define REG_SIZE 0x04 75 #define REG_SOC_WMSK 0xffff0000 76 #define CLK_GATE_MASK 0x01 77 78 #define PMUCRU_GATE_COUNT 0x03 79 #define CRU_GATE_COUNT 0x23 80 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 81 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 82 83 enum plls_id { 84 ALPLL_ID = 0, 85 ABPLL_ID, 86 DPLL_ID, 87 CPLL_ID, 88 GPLL_ID, 89 NPLL_ID, 90 VPLL_ID, 91 PPLL_ID, 92 END_PLL_ID, 93 }; 94 95 #define CLST_L_CPUS_MSK (0xf) 96 #define CLST_B_CPUS_MSK (0x3) 97 98 enum pll_work_mode { 99 SLOW_MODE = 0x00, 100 NORMAL_MODE = 0x01, 101 DEEP_SLOW_MODE = 0x02, 102 }; 103 104 enum glb_sft_reset { 105 PMU_RST_BY_FIRST_SFT, 106 PMU_RST_BY_SECOND_SFT = BIT(2), 107 PMU_RST_NOT_BY_SFT = BIT(3), 108 }; 109 110 struct pll_div { 111 uint32_t mhz; 112 uint32_t refdiv; 113 uint32_t fbdiv; 114 uint32_t postdiv1; 115 uint32_t postdiv2; 116 uint32_t frac; 117 uint32_t freq; 118 }; 119 120 struct deepsleep_data_s { 121 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 122 uint32_t cru_gate_con[CRU_GATE_COUNT]; 123 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 124 }; 125 126 /************************************************** 127 * pmugrf reg, offset 128 **************************************************/ 129 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 130 131 /************************************************** 132 * DCF reg, offset 133 **************************************************/ 134 #define DCF_DCF_CTRL 0x0 135 #define DCF_DCF_ADDR 0x8 136 #define DCF_DCF_ISR 0xc 137 #define DCF_DCF_TOSET 0x14 138 #define DCF_DCF_TOCMD 0x18 139 #define DCF_DCF_CMD_CFG 0x1c 140 141 /* DCF_DCF_ISR */ 142 #define DCF_TIMEOUT (1 << 2) 143 #define DCF_ERR (1 << 1) 144 #define DCF_DONE (1 << 0) 145 146 /* DCF_DCF_CTRL */ 147 #define DCF_VOP_HW_EN (1 << 2) 148 #define DCF_STOP (1 << 1) 149 #define DCF_START (1 << 0) 150 151 #define CYCL_24M_CNT_US(us) (24 * us) 152 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 153 #define CYCL_32K_CNT_MS(ms) (ms * 32) 154 155 /************************************************** 156 * cru reg, offset 157 **************************************************/ 158 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 159 160 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 161 /* reset release*/ 162 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 163 164 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 165 /* reset release*/ 166 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 167 168 #define CRU_GLB_RST_CON 0x0510 169 #define CRU_GLB_SRST_FST 0x0500 170 #define CRU_GLB_SRST_SND 0x0504 171 172 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 173 #define PCLK_GPIO2_GATE_SHIFT 3 174 #define PCLK_GPIO3_GATE_SHIFT 4 175 #define PCLK_GPIO4_GATE_SHIFT 5 176 177 /************************************************** 178 * pmu cru reg, offset 179 **************************************************/ 180 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 181 /* reset hold*/ 182 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 183 /* reset hold release*/ 184 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 185 186 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 187 #define CRU_PMU_WDTRST_EN 0x0 188 189 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 190 #define CRU_PMU_FIRST_SFTRST_EN 0x0 191 192 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 193 #define PCLK_GPIO0_GATE_SHIFT 3 194 #define PCLK_GPIO1_GATE_SHIFT 4 195 196 #define CPU_BOOT_ADDR_WMASK 0xffff0000 197 #define CPU_BOOT_ADDR_ALIGN 16 198 199 #define GRF_IOMUX_2BIT_MASK 0x3 200 #define GRF_IOMUX_GPIO 0x0 201 202 #define GRF_GPIO4C2_IOMUX_SHIFT 4 203 #define GRF_GPIO4C2_IOMUX_PWM 0x1 204 #define GRF_GPIO4C6_IOMUX_SHIFT 12 205 #define GRF_GPIO4C6_IOMUX_PWM 0x1 206 207 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 208 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 209 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 210 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 211 212 #define PWM_DISABLE (0 << 0) 213 #define PWM_ENABLE (1 << 0) 214 215 /* grf reg offset */ 216 #define GRF_DDRC0_CON0 0xe380 217 #define GRF_DDRC0_CON1 0xe384 218 #define GRF_DDRC1_CON0 0xe388 219 #define GRF_DDRC1_CON1 0xe38c 220 #define GRF_SOC_CON_BASE 0xe200 221 #define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) 222 223 #define PMUCRU_CLKSEL_CON0 0x0080 224 #define PMUCRU_CLKGATE_CON2 0x0108 225 #define PMUCRU_SOFTRST_CON0 0x0110 226 #define PMUCRU_GATEDIS_CON0 0x0130 227 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) 228 229 /* 230 * When system reset in running state, we want the cpus to be reboot 231 * from maskrom (system reboot), 232 * the pmusgrf reset-hold bits needs to be released. 233 * When system wake up from system deep suspend, some soc will be reset 234 * when waked up, 235 * we want the bootcpu to be reboot from pmusram, 236 * the pmusgrf reset-hold bits needs to be held. 237 */ 238 static inline void pmu_sgrf_rst_hld_release(void) 239 { 240 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 241 CRU_PMU_SGRF_RST_RLS); 242 } 243 244 static inline void pmu_sgrf_rst_hld(void) 245 { 246 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 247 CRU_PMU_SGRF_RST_HOLD); 248 } 249 250 /* export related and operating SoC APIs */ 251 void __dead2 soc_global_soft_reset(void); 252 void disable_dvfs_plls(void); 253 void disable_nodvfs_plls(void); 254 void enable_dvfs_plls(void); 255 void enable_nodvfs_plls(void); 256 void prepare_abpll_for_ddrctrl(void); 257 void restore_abpll(void); 258 void restore_dpll(void); 259 void clk_gate_con_save(void); 260 void clk_gate_con_disable(void); 261 void clk_gate_con_restore(void); 262 263 #endif /* __SOC_H__ */ 264