1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #define GLB_SRST_FST_CFG_VAL 0xfdb9 35 #define GLB_SRST_SND_CFG_VAL 0xeca8 36 37 #define PMUCRU_PPLL_CON(n) ((n) * 4) 38 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 39 #define PLL_MODE_MSK 0x03 40 #define PLL_MODE_SHIFT 0x08 41 #define PLL_BYPASS_MSK 0x01 42 #define PLL_BYPASS_SHIFT 0x01 43 #define PLL_PWRDN_MSK 0x01 44 #define PLL_PWRDN_SHIFT 0x0 45 #define PLL_BYPASS BIT(1) 46 #define PLL_PWRDN BIT(0) 47 48 #define NO_PLL_BYPASS (0x00) 49 #define NO_PLL_PWRDN (0x00) 50 51 #define FBDIV(n) ((0xfff << 16) | n) 52 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 53 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 54 #define REFDIV(n) ((0x3F << 16) | n) 55 #define PLL_LOCK(n) ((n >> 31) & 0x1) 56 57 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 58 PLL_MODE_MSK, PLL_MODE_SHIFT) 59 60 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 61 PLL_MODE_MSK, PLL_MODE_SHIFT) 62 63 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 64 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 65 66 #define PLL_CON_COUNT 0x06 67 #define CRU_CLKSEL_COUNT 0x108 68 #define CRU_CLKSEL_CON(n) (0x80 + (n) * 4) 69 70 #define PMUCRU_CLKSEL_CONUT 0x06 71 #define PMUCRU_CLKSEL_OFFSET 0x080 72 #define REG_SIZE 0x04 73 #define REG_SOC_WMSK 0xffff0000 74 #define CLK_GATE_MASK 0x01 75 76 #define PMUCRU_GATE_COUNT 0x03 77 #define CRU_GATE_COUNT 0x23 78 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 79 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 80 81 enum plls_id { 82 ALPLL_ID = 0, 83 ABPLL_ID, 84 DPLL_ID, 85 CPLL_ID, 86 GPLL_ID, 87 NPLL_ID, 88 VPLL_ID, 89 PPLL_ID, 90 END_PLL_ID, 91 }; 92 93 #define CLST_L_CPUS_MSK (0xf) 94 #define CLST_B_CPUS_MSK (0x3) 95 96 enum pll_work_mode { 97 SLOW_MODE = 0x00, 98 NORMAL_MODE = 0x01, 99 DEEP_SLOW_MODE = 0x02, 100 }; 101 102 enum glb_sft_reset { 103 PMU_RST_BY_FIRST_SFT, 104 PMU_RST_BY_SECOND_SFT = BIT(2), 105 PMU_RST_NOT_BY_SFT = BIT(3), 106 }; 107 108 struct deepsleep_data_s { 109 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 110 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 111 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 112 uint32_t cru_gate_con[CRU_GATE_COUNT]; 113 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 114 }; 115 116 /************************************************** 117 * pmugrf reg, offset 118 **************************************************/ 119 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 120 121 /************************************************** 122 * DCF reg, offset 123 **************************************************/ 124 #define DCF_DCF_CTRL 0x0 125 #define DCF_DCF_ADDR 0x8 126 #define DCF_DCF_ISR 0xc 127 #define DCF_DCF_TOSET 0x14 128 #define DCF_DCF_TOCMD 0x18 129 #define DCF_DCF_CMD_CFG 0x1c 130 131 /* DCF_DCF_ISR */ 132 #define DCF_TIMEOUT (1 << 2) 133 #define DCF_ERR (1 << 1) 134 #define DCF_DONE (1 << 0) 135 136 /* DCF_DCF_CTRL */ 137 #define DCF_VOP_HW_EN (1 << 2) 138 #define DCF_STOP (1 << 1) 139 #define DCF_START (1 << 0) 140 141 #define CYCL_24M_CNT_US(us) (24 * us) 142 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 143 #define CYCL_32K_CNT_MS(ms) (ms * 32) 144 145 /************************************************** 146 * secure timer 147 **************************************************/ 148 149 /* chanal0~5 */ 150 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 151 /* chanal6~11 */ 152 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 153 154 /* low 32 bits */ 155 #define TIMER_END_COUNT0 0x00 156 /* high 32 bits */ 157 #define TIMER_END_COUNT1 0x04 158 159 #define TIMER_CURRENT_VALUE0 0x08 160 #define TIMER_CURRENT_VALUE1 0x0C 161 162 /* low 32 bits */ 163 #define TIMER_INIT_COUNT0 0x10 164 /* high 32 bits */ 165 #define TIMER_INIT_COUNT1 0x14 166 167 #define TIMER_INTSTATUS 0x18 168 #define TIMER_CONTROL_REG 0x1c 169 170 #define TIMER_EN 0x1 171 172 #define TIMER_FMODE (0x0 << 1) 173 #define TIMER_RMODE (0x1 << 1) 174 175 /************************************************** 176 * cru reg, offset 177 **************************************************/ 178 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 179 180 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 181 /* reset release*/ 182 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 183 184 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 185 /* reset release*/ 186 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 187 188 #define CRU_GLB_RST_CON 0x0510 189 #define CRU_GLB_SRST_FST 0x0500 190 #define CRU_GLB_SRST_SND 0x0504 191 192 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 193 #define PCLK_GPIO2_GATE_SHIFT 3 194 #define PCLK_GPIO3_GATE_SHIFT 4 195 #define PCLK_GPIO4_GATE_SHIFT 5 196 197 /************************************************** 198 * pmu cru reg, offset 199 **************************************************/ 200 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 201 /* reset hold*/ 202 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 203 /* reset hold release*/ 204 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 205 206 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 207 #define CRU_PMU_WDTRST_EN 0x0 208 209 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 210 #define CRU_PMU_FIRST_SFTRST_EN 0x0 211 212 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 213 #define PCLK_GPIO0_GATE_SHIFT 3 214 #define PCLK_GPIO1_GATE_SHIFT 4 215 216 /************************************************** 217 * sgrf reg, offset 218 **************************************************/ 219 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 220 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 221 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 222 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 223 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 224 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 225 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 226 227 /* security config for master */ 228 #define SGRF_SOC_CON_WMSK 0xffff0000 229 /* All of master in ns */ 230 #define SGRF_SOC_ALLMST_NS 0xffff 231 232 /* security config for slave */ 233 #define SGRF_SLV_S_WMSK 0xffff0000 234 #define SGRF_SLV_S_ALL_NS 0x0 235 236 /* security config pmu slave ip */ 237 /* All of slaves is ns */ 238 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 239 /* slaves secure attr is configed */ 240 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 241 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 242 243 #define SGRF_PMUSRAM_S BIT(8) 244 245 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 246 SGRF_PMUSRAM_S) 247 /* ddr region */ 248 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 249 250 /* The MST access the ddr rgn n with secure attribution */ 251 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 252 /* bits[16:8]*/ 253 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 254 255 /* dmac to periph s or ns*/ 256 #define SGRF_DMAC_CFG_S 0xffff0000 257 258 #define DMAC1_RGN_NS 0xff000000 259 #define DMAC0_RGN_NS 0x00ff0000 260 261 #define DMAC0_BOOT_CFG_NS 0xfffffff8 262 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 263 #define DMAC0_BOOT_ADDR_NS 0xffff0000 264 265 #define DMAC1_BOOT_CFG_NS 0xffff0008 266 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 267 #define DMAC1_BOOT_ADDR_NS 0xffff0000 268 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 269 #define DMAC1_BOOT_IRQ_NS 0xffffffff 270 271 #define CPU_BOOT_ADDR_WMASK 0xffff0000 272 #define CPU_BOOT_ADDR_ALIGN 16 273 274 #define GRF_IOMUX_2BIT_MASK 0x3 275 #define GRF_IOMUX_GPIO 0x0 276 277 #define GRF_GPIO4C2_IOMUX_SHIFT 4 278 #define GRF_GPIO4C2_IOMUX_PWM 0x1 279 #define GRF_GPIO4C6_IOMUX_SHIFT 12 280 #define GRF_GPIO4C6_IOMUX_PWM 0x1 281 282 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 283 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 284 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 285 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 286 287 #define PWM_DISABLE (0 << 0) 288 #define PWM_ENABLE (1 << 0) 289 290 /* grf reg offset */ 291 #define GRF_DDRC0_CON0 0xe380 292 #define GRF_DDRC0_CON1 0xe384 293 #define GRF_DDRC1_CON0 0xe388 294 #define GRF_DDRC1_CON1 0xe38c 295 296 /* 297 * When system reset in running state, we want the cpus to be reboot 298 * from maskrom (system reboot), 299 * the pmusgrf reset-hold bits needs to be released. 300 * When system wake up from system deep suspend, some soc will be reset 301 * when waked up, 302 * we want the bootcpu to be reboot from pmusram, 303 * the pmusgrf reset-hold bits needs to be held. 304 */ 305 static inline void pmu_sgrf_rst_hld_release(void) 306 { 307 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 308 CRU_PMU_SGRF_RST_RLS); 309 } 310 311 static inline void pmu_sgrf_rst_hld(void) 312 { 313 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 314 CRU_PMU_SGRF_RST_HOLD); 315 } 316 317 /* funciton*/ 318 void __dead2 soc_global_soft_reset(void); 319 void plls_suspend_prepare(void); 320 void disable_dvfs_plls(void); 321 void disable_nodvfs_plls(void); 322 void plls_resume_finish(void); 323 void enable_dvfs_plls(void); 324 void enable_nodvfs_plls(void); 325 void clk_gate_con_save(void); 326 void clk_gate_con_disable(void); 327 void clk_gate_con_restore(void); 328 #endif /* __SOC_H__ */ 329