1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ 32 #define __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ 33 34 /************************************************** 35 * sgrf reg, offset 36 **************************************************/ 37 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 38 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 39 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 40 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ 41 (n < 8 ? SGRF_SOC_CON3_7(n) :\ 42 SGRF_SOC_CON8_15(n))) 43 44 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 45 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 46 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 47 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 48 49 /* All of master in ns */ 50 #define SGRF_SOC_ALLMST_NS 0xffff 51 52 /* security config for slave */ 53 #define SGRF_SLV_S_WMSK 0xffff0000 54 #define SGRF_SLV_S_ALL_NS 0x0 55 56 /* security config pmu slave ip */ 57 /* All of slaves is ns */ 58 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 59 /* slaves secure attr is configed */ 60 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 61 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 62 63 #define SGRF_PMUSRAM_S BIT(8) 64 65 /* ddr region */ 66 #define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */ 67 68 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ 69 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ 70 71 /* All security of the DDR RGNs are bypass */ 72 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) 73 /* All security of the DDR RGNs are not bypass */ 74 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9) 75 76 /* The MST access the ddr rgn n with secure attribution */ 77 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 78 /* bits[16:8]*/ 79 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 80 81 #define SGRF_PMU_CON0 0x0c100 82 #define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) 83 84 /************************************************** 85 * secure timer 86 **************************************************/ 87 /* chanal0~5 */ 88 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 89 /* chanal6~11 */ 90 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 91 92 /* low 32 bits */ 93 #define TIMER_END_COUNT0 0x00 94 /* high 32 bits */ 95 #define TIMER_END_COUNT1 0x04 96 97 #define TIMER_CURRENT_VALUE0 0x08 98 #define TIMER_CURRENT_VALUE1 0x0C 99 100 /* low 32 bits */ 101 #define TIMER_INIT_COUNT0 0x10 102 /* high 32 bits */ 103 #define TIMER_INIT_COUNT1 0x14 104 105 #define TIMER_INTSTATUS 0x18 106 #define TIMER_CONTROL_REG 0x1c 107 108 #define TIMER_EN 0x1 109 110 #define TIMER_FMODE (0x0 << 1) 111 #define TIMER_RMODE (0x1 << 1) 112 113 /************************************************** 114 * secure WDT 115 **************************************************/ 116 #define PCLK_WDT_CA53_GATE_SHIFT 8 117 #define PCLK_WDT_CM0_GATE_SHIFT 10 118 119 /* export secure operating APIs */ 120 void secure_watchdog_disable(void); 121 void secure_watchdog_enable(void); 122 void secure_timer_init(void); 123 void secure_sgrf_init(void); 124 void secure_sgrf_ddr_rgn_init(void); 125 126 #endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */ 127