1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 13 #include <plat_private.h> 14 #include <secure.h> 15 #include <soc.h> 16 17 static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) 18 { 19 if (bypass) 20 /* set bypass (non-secure regions) for whole ddr regions */ 21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 22 SGRF_DDR_RGN_BYPS); 23 else 24 /* cancel bypass for whole ddr regions */ 25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 26 SGRF_DDR_RGN_NO_BYPS); 27 } 28 29 /** 30 * There are 8 + 1 regions for DDR secure control: 31 * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB 32 * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7 33 * 34 * DDR_RGN_0 - start address of the RGN0 35 * DDR_RGN_8 - end address of the RGN0 36 * DDR_RGN_1 - start address of the RGN1 37 * DDR_RGN_9 - end address of the RGN1 38 * ... 39 * DDR_RGN_7 - start address of the RGN7 40 * DDR_RGN_15 - end address of the RGN7 41 * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable 42 * bit 8 is setting for RGNx, the rest of the memory and region 43 * which excludes RGN0~7, 0: disable, 1: enable 44 * bit 9, the global secure configuration via bypass, 0: disable 45 * bypass, 1: enable bypass 46 * 47 * @rgn - the DDR regions 0 ~ 7 which are can be configured. 48 * The @st_mb and @ed_mb indicate the start and end addresses for which to set 49 * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the 50 * address range 0x0 ~ 0xfffff is secure. 51 * 52 * For example, if we would like to set the range [0, 32MB) is security via 53 * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. 54 */ 55 static void sgrf_ddr_rgn_config(uint32_t rgn, 56 uintptr_t st, uintptr_t ed) 57 { 58 uintptr_t st_mb, ed_mb; 59 60 assert(rgn <= 7); 61 assert(st < ed); 62 63 /* check aligned 1MB */ 64 assert(st % SIZE_M(1) == 0); 65 assert(ed % SIZE_M(1) == 0); 66 67 st_mb = st / SIZE_M(1); 68 ed_mb = ed / SIZE_M(1); 69 70 /* set ddr region addr start */ 71 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), 72 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); 73 74 /* set ddr region addr end */ 75 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), 76 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); 77 78 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 79 BIT_WITH_WMSK(rgn)); 80 } 81 82 void secure_watchdog_gate(void) 83 { 84 /** 85 * Disable CA53 and CM0 wdt pclk 86 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable 87 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable 88 */ 89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 90 BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) | 91 BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT)); 92 } 93 94 __pmusramfunc void secure_watchdog_ungate(void) 95 { 96 /** 97 * Enable CA53 and CM0 wdt pclk 98 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable 99 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable 100 */ 101 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 102 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | 103 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); 104 } 105 106 __pmusramfunc void sram_secure_timer_init(void) 107 { 108 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 109 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 110 111 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 112 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 113 114 /* auto reload & enable the timer */ 115 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 116 TIMER_EN | TIMER_FMODE); 117 } 118 119 void secure_timer_init(void) 120 { 121 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 122 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 123 124 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 125 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 126 127 /* auto reload & enable the timer */ 128 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 129 TIMER_EN | TIMER_FMODE); 130 } 131 132 void secure_sgrf_init(void) 133 { 134 /* security config for master */ 135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), 136 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 137 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), 138 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 139 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), 140 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 141 142 /* security config for slave */ 143 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 144 SGRF_PMU_SLV_S_CFGED | 145 SGRF_PMU_SLV_CRYPTO1_NS); 146 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 147 SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S); 148 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 149 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 150 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 151 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 152 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 153 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 154 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 155 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 156 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 157 SGRF_SLV_S_WMSK | SGRF_INTSRAM_S); 158 } 159 160 void secure_sgrf_ddr_rgn_init(void) 161 { 162 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); 163 sgrf_ddr_rgn_global_bypass(0); 164 } 165