1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <plat_private.h> 36 #include <secure.h> 37 #include <soc.h> 38 39 static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) 40 { 41 if (bypass) 42 /* set bypass (non-secure regions) for whole ddr regions */ 43 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 44 SGRF_DDR_RGN_BYPS); 45 else 46 /* cancel bypass for whole ddr regions */ 47 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 48 SGRF_DDR_RGN_NO_BYPS); 49 } 50 51 /** 52 * There are 8 + 1 regions for DDR secure control: 53 * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB 54 * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7 55 * 56 * DDR_RGN_0 - start address of the RGN0 57 * DDR_RGN_8 - end address of the RGN0 58 * DDR_RGN_1 - start address of the RGN1 59 * DDR_RGN_9 - end address of the RGN1 60 * ... 61 * DDR_RGN_7 - start address of the RGN7 62 * DDR_RGN_15 - end address of the RGN7 63 * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable 64 * bit 8 is setting for RGNx, the rest of the memory and region 65 * which excludes RGN0~7, 0: disable, 1: enable 66 * bit 9, the global secure configuration via bypass, 0: disable 67 * bypass, 1: enable bypass 68 * 69 * @rgn - the DDR regions 0 ~ 7 which are can be configured. 70 * The @st_mb and @ed_mb indicate the start and end addresses for which to set 71 * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the 72 * address range 0x0 ~ 0xfffff is secure. 73 * 74 * For example, if we would like to set the range [0, 32MB) is security via 75 * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. 76 */ 77 static void sgrf_ddr_rgn_config(uint32_t rgn, 78 uintptr_t st, uintptr_t ed) 79 { 80 uintptr_t st_mb, ed_mb; 81 82 assert(rgn <= 7); 83 assert(st < ed); 84 85 /* check aligned 1MB */ 86 assert(st % SIZE_M(1) == 0); 87 assert(ed % SIZE_M(1) == 0); 88 89 st_mb = st / SIZE_M(1); 90 ed_mb = ed / SIZE_M(1); 91 92 /* set ddr region addr start */ 93 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), 94 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); 95 96 /* set ddr region addr end */ 97 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), 98 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); 99 100 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 101 BIT_WITH_WMSK(rgn)); 102 } 103 104 void secure_watchdog_disable(void) 105 { 106 /** 107 * Disable CA53 and CM0 wdt pclk 108 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable 109 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable 110 */ 111 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 112 BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) | 113 BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT)); 114 } 115 116 void secure_watchdog_enable(void) 117 { 118 /** 119 * Enable CA53 and CM0 wdt pclk 120 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable 121 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable 122 */ 123 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 124 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | 125 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); 126 } 127 128 void secure_timer_init(void) 129 { 130 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 131 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 132 133 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 134 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 135 136 /* auto reload & enable the timer */ 137 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 138 TIMER_EN | TIMER_FMODE); 139 } 140 141 void secure_sgrf_init(void) 142 { 143 /* security config for master */ 144 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), 145 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 146 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), 147 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 148 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), 149 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); 150 151 /* security config for slave */ 152 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 153 SGRF_PMU_SLV_S_CFGED | 154 SGRF_PMU_SLV_CRYPTO1_NS); 155 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 156 SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S); 157 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 158 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 159 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 160 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 161 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 162 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 163 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 164 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 165 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 166 SGRF_SLV_S_WMSK | SGRF_INTSRAM_S); 167 } 168 169 void secure_sgrf_ddr_rgn_init(void) 170 { 171 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); 172 sgrf_ddr_rgn_global_bypass(0); 173 } 174