1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <plat_private.h> 32 #include <pmu.h> 33 #include <pwm.h> 34 #include <soc.h> 35 36 #define PWM0_IOMUX_PWM_EN (1 << 0) 37 #define PWM1_IOMUX_PWM_EN (1 << 1) 38 #define PWM2_IOMUX_PWM_EN (1 << 2) 39 #define PWM3_IOMUX_PWM_EN (1 << 3) 40 41 struct pwm_data_s { 42 uint32_t iomux_bitmask; 43 uint32_t enable_bitmask; 44 }; 45 46 static struct pwm_data_s pwm_data; 47 48 /* 49 * Disable the PWMs. 50 */ 51 void disable_pwms(void) 52 { 53 uint32_t i, val; 54 55 pwm_data.iomux_bitmask = 0; 56 57 /* Save PWMs pinmux and change PWMs pinmux to GPIOs */ 58 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); 59 if (((val >> GRF_GPIO4C2_IOMUX_SHIFT) & 60 GRF_IOMUX_2BIT_MASK) == GRF_GPIO4C2_IOMUX_PWM) { 61 pwm_data.iomux_bitmask |= PWM0_IOMUX_PWM_EN; 62 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, 63 GRF_GPIO4C2_IOMUX_SHIFT); 64 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); 65 } 66 67 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); 68 if (((val >> GRF_GPIO4C6_IOMUX_SHIFT) & 69 GRF_IOMUX_2BIT_MASK) == GRF_GPIO4C6_IOMUX_PWM) { 70 pwm_data.iomux_bitmask |= PWM1_IOMUX_PWM_EN; 71 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, 72 GRF_GPIO4C6_IOMUX_SHIFT); 73 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); 74 } 75 76 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); 77 if (((val >> PMUGRF_GPIO1C3_IOMUX_SHIFT) & 78 GRF_IOMUX_2BIT_MASK) == PMUGRF_GPIO1C3_IOMUX_PWM) { 79 pwm_data.iomux_bitmask |= PWM2_IOMUX_PWM_EN; 80 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, 81 PMUGRF_GPIO1C3_IOMUX_SHIFT); 82 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); 83 } 84 85 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX); 86 if (((val >> PMUGRF_GPIO0A6_IOMUX_SHIFT) & 87 GRF_IOMUX_2BIT_MASK) == PMUGRF_GPIO0A6_IOMUX_PWM) { 88 pwm_data.iomux_bitmask |= PWM3_IOMUX_PWM_EN; 89 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, 90 PMUGRF_GPIO0A6_IOMUX_SHIFT); 91 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); 92 } 93 94 /* Disable the pwm channel */ 95 pwm_data.enable_bitmask = 0; 96 for (i = 0; i < 4; i++) { 97 val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); 98 if ((val & PWM_ENABLE) != PWM_ENABLE) 99 continue; 100 pwm_data.enable_bitmask |= (1 << i); 101 mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE); 102 } 103 } 104 105 /* 106 * Enable the PWMs. 107 */ 108 void enable_pwms(void) 109 { 110 uint32_t i, val; 111 112 for (i = 0; i < 4; i++) { 113 val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); 114 if (!(pwm_data.enable_bitmask & (1 << i))) 115 continue; 116 mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE); 117 } 118 119 /* Restore all IOMUXes */ 120 if (pwm_data.iomux_bitmask & PWM3_IOMUX_PWM_EN) { 121 val = BITS_WITH_WMASK(PMUGRF_GPIO0A6_IOMUX_PWM, 122 GRF_IOMUX_2BIT_MASK, 123 PMUGRF_GPIO0A6_IOMUX_SHIFT); 124 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); 125 } 126 127 if (pwm_data.iomux_bitmask & PWM2_IOMUX_PWM_EN) { 128 val = BITS_WITH_WMASK(PMUGRF_GPIO1C3_IOMUX_PWM, 129 GRF_IOMUX_2BIT_MASK, 130 PMUGRF_GPIO1C3_IOMUX_SHIFT); 131 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); 132 } 133 134 if (pwm_data.iomux_bitmask & PWM1_IOMUX_PWM_EN) { 135 val = BITS_WITH_WMASK(GRF_GPIO4C6_IOMUX_PWM, 136 GRF_IOMUX_2BIT_MASK, 137 GRF_GPIO4C6_IOMUX_SHIFT); 138 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); 139 } 140 141 if (pwm_data.iomux_bitmask & PWM0_IOMUX_PWM_EN) { 142 val = BITS_WITH_WMASK(GRF_GPIO4C2_IOMUX_PWM, 143 GRF_IOMUX_2BIT_MASK, 144 GRF_GPIO4C2_IOMUX_SHIFT); 145 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); 146 } 147 } 148