1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_H__ 32 #define __PMU_H__ 33 34 /* Allocate sp reginon in pmusram */ 35 #define PSRAM_SP_SIZE 0x80 36 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 37 38 /***************************************************************************** 39 * Common define for per soc pmu.h 40 *****************************************************************************/ 41 /* The ways of cores power domain contorlling */ 42 enum cores_pm_ctr_mode { 43 core_pwr_pd = 0, 44 core_pwr_wfi = 1, 45 core_pwr_wfi_int = 2 46 }; 47 48 /***************************************************************************** 49 * pmu con,reg 50 *****************************************************************************/ 51 #define PMU_WKUP_CFG(n) ((n) * 4) 52 53 #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) 54 55 /* the shift of bits for cores status */ 56 enum pmu_core_pwrst_shift { 57 clstl_cpu_wfe = 2, 58 clstl_cpu_wfi = 6, 59 clstb_cpu_wfe = 12, 60 clstb_cpu_wfi = 16 61 }; 62 63 #define CKECK_WFE_MSK 0x1 64 #define CKECK_WFI_MSK 0x10 65 #define CKECK_WFEI_MSK 0x11 66 67 enum pmu_powerdomain_id { 68 PD_CPUL0 = 0, 69 PD_CPUL1, 70 PD_CPUL2, 71 PD_CPUL3, 72 PD_CPUB0, 73 PD_CPUB1, 74 PD_SCUL, 75 PD_SCUB, 76 PD_TCPD0, 77 PD_TCPD1, 78 PD_CCI, 79 PD_PERILP, 80 PD_PERIHP, 81 PD_CENTER, 82 PD_VIO, 83 PD_GPU, 84 PD_VCODEC, 85 PD_VDU, 86 PD_RGA, 87 PD_IEP, 88 PD_VO, 89 PD_ISP0 = 22, 90 PD_ISP1, 91 PD_HDCP, 92 PD_GMAC, 93 PD_EMMC, 94 PD_USB3, 95 PD_EDP, 96 PD_GIC, 97 PD_SD, 98 PD_SDIOAUDIO, 99 PD_END 100 }; 101 102 enum powerdomain_state { 103 PMU_POWER_ON = 0, 104 PMU_POWER_OFF, 105 }; 106 107 enum pmu_bus_id { 108 BUS_ID_GPU = 0, 109 BUS_ID_PERILP, 110 BUS_ID_PERIHP, 111 BUS_ID_VCODEC, 112 BUS_ID_VDU, 113 BUS_ID_RGA, 114 BUS_ID_IEP, 115 BUS_ID_VOPB, 116 BUS_ID_VOPL, 117 BUS_ID_ISP0, 118 BUS_ID_ISP1, 119 BUS_ID_HDCP, 120 BUS_ID_USB3, 121 BUS_ID_PERILPM0, 122 BUS_ID_CENTER, 123 BUS_ID_CCIM0, 124 BUS_ID_CCIM1, 125 BUS_ID_VIO, 126 BUS_ID_MSCH0, 127 BUS_ID_MSCH1, 128 BUS_ID_ALIVE, 129 BUS_ID_PMU, 130 BUS_ID_EDP, 131 BUS_ID_GMAC, 132 BUS_ID_EMMC, 133 BUS_ID_CENTER1, 134 BUS_ID_PMUM0, 135 BUS_ID_GIC, 136 BUS_ID_SD, 137 BUS_ID_SDIOAUDIO, 138 }; 139 140 enum pmu_bus_state { 141 BUS_ACTIVE, 142 BUS_IDLE, 143 }; 144 145 /* pmu_cpuapm bit */ 146 enum pmu_cores_pm_by_wfi { 147 core_pm_en = 0, 148 core_pm_int_wakeup_en, 149 core_pm_resv, 150 core_pm_sft_wakeup_en 151 }; 152 153 enum pmu_wkup_cfg0 { 154 PMU_GPIO0A_POSE_WKUP_EN = 0, 155 PMU_GPIO0B_POSE_WKUP_EN = 8, 156 PMU_GPIO0C_POSE_WKUP_EN = 16, 157 PMU_GPIO0D_POSE_WKUP_EN = 24, 158 }; 159 160 enum pmu_wkup_cfg1 { 161 PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, 162 PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, 163 PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, 164 PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, 165 }; 166 167 enum pmu_wkup_cfg2 { 168 PMU_GPIO1A_POSE_WKUP_EN = 0, 169 PMU_GPIO1B_POSE_WKUP_EN = 7, 170 PMU_GPIO1C_POSE_WKUP_EN = 16, 171 PMU_GPIO1D_POSE_WKUP_EN = 24, 172 }; 173 174 enum pmu_wkup_cfg3 { 175 PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, 176 PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, 177 PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, 178 PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, 179 }; 180 181 /* pmu_wkup_cfg4 */ 182 enum pmu_wkup_cfg4 { 183 PMU_CLUSTER_L_WKUP_EN = 0, 184 PMU_CLUSTER_B_WKUP_EN, 185 PMU_GPIO_WKUP_EN, 186 PMU_SDIO_WKUP_EN, 187 188 PMU_SDMMC_WKUP_EN, 189 PMU_TIMER_WKUP_EN = 6, 190 PMU_USBDEV_WKUP_EN, 191 192 PMU_SFT_WKUP_EN, 193 PMU_M0_WDT_WKUP_EN, 194 PMU_TIMEOUT_WKUP_EN, 195 PMU_PWM_WKUP_EN, 196 197 PMU_PCIE_WKUP_EN = 13, 198 }; 199 200 enum pmu_pwrdn_con { 201 PMU_A53_L0_PWRDWN_EN = 0, 202 PMU_A53_L1_PWRDWN_EN, 203 PMU_A53_L2_PWRDWN_EN, 204 PMU_A53_L3_PWRDWN_EN, 205 206 PMU_A72_B0_PWRDWN_EN, 207 PMU_A72_B1_PWRDWN_EN, 208 PMU_SCU_L_PWRDWN_EN, 209 PMU_SCU_B_PWRDWN_EN, 210 211 PMU_TCPD0_PWRDWN_EN, 212 PMU_TCPD1_PWRDWN_EN, 213 PMU_CCI_PWRDWN_EN, 214 PMU_PERILP_PWRDWN_EN, 215 216 PMU_PERIHP_PWRDWN_EN, 217 PMU_CENTER_PWRDWN_EN, 218 PMU_VIO_PWRDWN_EN, 219 PMU_GPU_PWRDWN_EN, 220 221 PMU_VCODEC_PWRDWN_EN, 222 PMU_VDU_PWRDWN_EN, 223 PMU_RGA_PWRDWN_EN, 224 PMU_IEP_PWRDWN_EN, 225 226 PMU_VO_PWRDWN_EN, 227 PMU_ISP0_PWRDWN_EN = 22, 228 PMU_ISP1_PWRDWN_EN, 229 230 PMU_HDCP_PWRDWN_EN, 231 PMU_GMAC_PWRDWN_EN, 232 PMU_EMMC_PWRDWN_EN, 233 PMU_USB3_PWRDWN_EN, 234 235 PMU_EDP_PWRDWN_EN, 236 PMU_GIC_PWRDWN_EN, 237 PMU_SD_PWRDWN_EN, 238 PMU_SDIOAUDIO_PWRDWN_EN, 239 }; 240 241 enum pmu_pwrdn_st { 242 PMU_A53_L0_PWRDWN_ST = 0, 243 PMU_A53_L1_PWRDWN_ST, 244 PMU_A53_L2_PWRDWN_ST, 245 PMU_A53_L3_PWRDWN_ST, 246 247 PMU_A72_B0_PWRDWN_ST, 248 PMU_A72_B1_PWRDWN_ST, 249 PMU_SCU_L_PWRDWN_ST, 250 PMU_SCU_B_PWRDWN_ST, 251 252 PMU_TCPD0_PWRDWN_ST, 253 PMU_TCPD1_PWRDWN_ST, 254 PMU_CCI_PWRDWN_ST, 255 PMU_PERILP_PWRDWN_ST, 256 257 PMU_PERIHP_PWRDWN_ST, 258 PMU_CENTER_PWRDWN_ST, 259 PMU_VIO_PWRDWN_ST, 260 PMU_GPU_PWRDWN_ST, 261 262 PMU_VCODEC_PWRDWN_ST, 263 PMU_VDU_PWRDWN_ST, 264 PMU_RGA_PWRDWN_ST, 265 PMU_IEP_PWRDWN_ST, 266 267 PMU_VO_PWRDWN_ST, 268 PMU_ISP0_PWRDWN_ST = 22, 269 PMU_ISP1_PWRDWN_ST, 270 271 PMU_HDCP_PWRDWN_ST, 272 PMU_GMAC_PWRDWN_ST, 273 PMU_EMMC_PWRDWN_ST, 274 PMU_USB3_PWRDWN_ST, 275 276 PMU_EDP_PWRDWN_ST, 277 PMU_GIC_PWRDWN_ST, 278 PMU_SD_PWRDWN_ST, 279 PMU_SDIOAUDIO_PWRDWN_ST, 280 281 }; 282 283 enum pmu_pll_con { 284 PMU_PLL_PD_CFG = 0, 285 PMU_SFT_PLL_PD = 8, 286 }; 287 288 enum pmu_pwermode_con { 289 PMU_PWR_MODE_EN = 0, 290 PMU_WKUP_RST_EN, 291 PMU_INPUT_CLAMP_EN, 292 PMU_OSC_DIS, 293 294 PMU_ALIVE_USE_LF, 295 PMU_PMU_USE_LF, 296 PMU_POWER_OFF_REQ_CFG, 297 PMU_CHIP_PD_EN, 298 299 PMU_PLL_PD_EN, 300 PMU_CPU0_PD_EN, 301 PMU_L2_FLUSH_EN, 302 PMU_L2_IDLE_EN, 303 304 PMU_SCU_PD_EN, 305 PMU_CCI_PD_EN, 306 PMU_PERILP_PD_EN, 307 PMU_CENTER_PD_EN, 308 309 PMU_SREF0_ENTER_EN, 310 PMU_DDRC0_GATING_EN, 311 PMU_DDRIO0_RET_EN, 312 PMU_DDRIO0_RET_DE_REQ, 313 314 PMU_SREF1_ENTER_EN, 315 PMU_DDRC1_GATING_EN, 316 PMU_DDRIO1_RET_EN, 317 PMU_DDRIO1_RET_DE_REQ, 318 319 PMU_CLK_CENTER_SRC_GATE_EN = 26, 320 PMU_CLK_PERILP_SRC_GATE_EN, 321 322 PMU_CLK_CORE_SRC_GATE_EN, 323 PMU_DDRIO_RET_HW_DE_REQ, 324 PMU_SLP_OUTPUT_CFG, 325 PMU_MAIN_CLUSTER, 326 }; 327 328 enum pmu_sft_con { 329 PMU_WKUP_SFT = 0, 330 PMU_INPUT_CLAMP_CFG, 331 PMU_OSC_DIS_CFG, 332 PMU_PMU_LF_EN_CFG, 333 334 PMU_ALIVE_LF_EN_CFG, 335 PMU_24M_EN_CFG, 336 PMU_DBG_PWRUP_L0_CFG, 337 PMU_WKUP_SFT_M0, 338 339 PMU_DDRCTL0_C_SYSREQ_CFG, 340 PMU_DDR0_IO_RET_CFG, 341 342 PMU_DDRCTL1_C_SYSREQ_CFG = 12, 343 PMU_DDR1_IO_RET_CFG, 344 }; 345 346 enum pmu_int_con { 347 PMU_PMU_INT_EN = 0, 348 PMU_PWRMD_WKUP_INT_EN, 349 PMU_WKUP_GPIO0_NEG_INT_EN, 350 PMU_WKUP_GPIO0_POS_INT_EN, 351 PMU_WKUP_GPIO1_NEG_INT_EN, 352 PMU_WKUP_GPIO1_POS_INT_EN, 353 }; 354 355 enum pmu_int_st { 356 PMU_PWRMD_WKUP_INT_ST = 1, 357 PMU_WKUP_GPIO0_NEG_INT_ST, 358 PMU_WKUP_GPIO0_POS_INT_ST, 359 PMU_WKUP_GPIO1_NEG_INT_ST, 360 PMU_WKUP_GPIO1_POS_INT_ST, 361 }; 362 363 enum pmu_gpio0_pos_int_con { 364 PMU_GPIO0A_POS_INT_EN = 0, 365 PMU_GPIO0B_POS_INT_EN = 8, 366 PMU_GPIO0C_POS_INT_EN = 16, 367 PMU_GPIO0D_POS_INT_EN = 24, 368 }; 369 370 enum pmu_gpio0_neg_int_con { 371 PMU_GPIO0A_NEG_INT_EN = 0, 372 PMU_GPIO0B_NEG_INT_EN = 8, 373 PMU_GPIO0C_NEG_INT_EN = 16, 374 PMU_GPIO0D_NEG_INT_EN = 24, 375 }; 376 377 enum pmu_gpio1_pos_int_con { 378 PMU_GPIO1A_POS_INT_EN = 0, 379 PMU_GPIO1B_POS_INT_EN = 8, 380 PMU_GPIO1C_POS_INT_EN = 16, 381 PMU_GPIO1D_POS_INT_EN = 24, 382 }; 383 384 enum pmu_gpio1_neg_int_con { 385 PMU_GPIO1A_NEG_INT_EN = 0, 386 PMU_GPIO1B_NEG_INT_EN = 8, 387 PMU_GPIO1C_NEG_INT_EN = 16, 388 PMU_GPIO1D_NEG_INT_EN = 24, 389 }; 390 391 enum pmu_gpio0_pos_int_st { 392 PMU_GPIO0A_POS_INT_ST = 0, 393 PMU_GPIO0B_POS_INT_ST = 8, 394 PMU_GPIO0C_POS_INT_ST = 16, 395 PMU_GPIO0D_POS_INT_ST = 24, 396 }; 397 398 enum pmu_gpio0_neg_int_st { 399 PMU_GPIO0A_NEG_INT_ST = 0, 400 PMU_GPIO0B_NEG_INT_ST = 8, 401 PMU_GPIO0C_NEG_INT_ST = 16, 402 PMU_GPIO0D_NEG_INT_ST = 24, 403 }; 404 405 enum pmu_gpio1_pos_int_st { 406 PMU_GPIO1A_POS_INT_ST = 0, 407 PMU_GPIO1B_POS_INT_ST = 8, 408 PMU_GPIO1C_POS_INT_ST = 16, 409 PMU_GPIO1D_POS_INT_ST = 24, 410 }; 411 412 enum pmu_gpio1_neg_int_st { 413 PMU_GPIO1A_NEG_INT_ST = 0, 414 PMU_GPIO1B_NEG_INT_ST = 8, 415 PMU_GPIO1C_NEG_INT_ST = 16, 416 PMU_GPIO1D_NEG_INT_ST = 24, 417 }; 418 419 /* pmu power down configure register 0x0050 */ 420 enum pmu_pwrdn_inten { 421 PMU_A53_L0_PWR_SWITCH_INT_EN = 0, 422 PMU_A53_L1_PWR_SWITCH_INT_EN, 423 PMU_A53_L2_PWR_SWITCH_INT_EN, 424 PMU_A53_L3_PWR_SWITCH_INT_EN, 425 426 PMU_A72_B0_PWR_SWITCH_INT_EN, 427 PMU_A72_B1_PWR_SWITCH_INT_EN, 428 PMU_SCU_L_PWR_SWITCH_INT_EN, 429 PMU_SCU_B_PWR_SWITCH_INT_EN, 430 431 PMU_TCPD0_PWR_SWITCH_INT_EN, 432 PMU_TCPD1_PWR_SWITCH_INT_EN, 433 PMU_CCI_PWR_SWITCH_INT_EN, 434 PMU_PERILP_PWR_SWITCH_INT_EN, 435 436 PMU_PERIHP_PWR_SWITCH_INT_EN, 437 PMU_CENTER_PWR_SWITCH_INT_EN, 438 PMU_VIO_PWR_SWITCH_INT_EN, 439 PMU_GPU_PWR_SWITCH_INT_EN, 440 441 PMU_VCODEC_PWR_SWITCH_INT_EN, 442 PMU_VDU_PWR_SWITCH_INT_EN, 443 PMU_RGA_PWR_SWITCH_INT_EN, 444 PMU_IEP_PWR_SWITCH_INT_EN, 445 446 PMU_VO_PWR_SWITCH_INT_EN, 447 PMU_ISP0_PWR_SWITCH_INT_EN = 22, 448 PMU_ISP1_PWR_SWITCH_INT_EN, 449 450 PMU_HDCP_PWR_SWITCH_INT_EN, 451 PMU_GMAC_PWR_SWITCH_INT_EN, 452 PMU_EMMC_PWR_SWITCH_INT_EN, 453 PMU_USB3_PWR_SWITCH_INT_EN, 454 455 PMU_EDP_PWR_SWITCH_INT_EN, 456 PMU_GIC_PWR_SWITCH_INT_EN, 457 PMU_SD_PWR_SWITCH_INT_EN, 458 PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, 459 }; 460 461 enum pmu_wkup_status { 462 PMU_WKUP_BY_CLSTER_L_INT = 0, 463 PMU_WKUP_BY_CLSTER_b_INT, 464 PMU_WKUP_BY_GPIO_INT, 465 PMU_WKUP_BY_SDIO_DET, 466 467 PMU_WKUP_BY_SDMMC_DET, 468 PMU_WKUP_BY_TIMER = 6, 469 PMU_WKUP_BY_USBDEV_DET, 470 471 PMU_WKUP_BY_M0_SFT, 472 PMU_WKUP_BY_M0_WDT_INT, 473 PMU_WKUP_BY_TIMEOUT, 474 PMU_WKUP_BY_PWM, 475 476 PMU_WKUP_BY_PCIE = 13, 477 }; 478 479 enum pmu_bus_clr { 480 PMU_CLR_GPU = 0, 481 PMU_CLR_PERILP, 482 PMU_CLR_PERIHP, 483 PMU_CLR_VCODEC, 484 485 PMU_CLR_VDU, 486 PMU_CLR_RGA, 487 PMU_CLR_IEP, 488 PMU_CLR_VOPB, 489 490 PMU_CLR_VOPL, 491 PMU_CLR_ISP0, 492 PMU_CLR_ISP1, 493 PMU_CLR_HDCP, 494 495 PMU_CLR_USB3, 496 PMU_CLR_PERILPM0, 497 PMU_CLR_CENTER, 498 PMU_CLR_CCIM1, 499 500 PMU_CLR_CCIM0, 501 PMU_CLR_VIO, 502 PMU_CLR_MSCH0, 503 PMU_CLR_MSCH1, 504 505 PMU_CLR_ALIVE, 506 PMU_CLR_PMU, 507 PMU_CLR_EDP, 508 PMU_CLR_GMAC, 509 510 PMU_CLR_EMMC, 511 PMU_CLR_CENTER1, 512 PMU_CLR_PMUM0, 513 PMU_CLR_GIC, 514 515 PMU_CLR_SD, 516 PMU_CLR_SDIOAUDIO, 517 }; 518 519 /* PMU bus idle request register */ 520 enum pmu_bus_idle_req { 521 PMU_IDLE_REQ_GPU = 0, 522 PMU_IDLE_REQ_PERILP, 523 PMU_IDLE_REQ_PERIHP, 524 PMU_IDLE_REQ_VCODEC, 525 526 PMU_IDLE_REQ_VDU, 527 PMU_IDLE_REQ_RGA, 528 PMU_IDLE_REQ_IEP, 529 PMU_IDLE_REQ_VOPB, 530 531 PMU_IDLE_REQ_VOPL, 532 PMU_IDLE_REQ_ISP0, 533 PMU_IDLE_REQ_ISP1, 534 PMU_IDLE_REQ_HDCP, 535 536 PMU_IDLE_REQ_USB3, 537 PMU_IDLE_REQ_PERILPM0, 538 PMU_IDLE_REQ_CENTER, 539 PMU_IDLE_REQ_CCIM0, 540 541 PMU_IDLE_REQ_CCIM1, 542 PMU_IDLE_REQ_VIO, 543 PMU_IDLE_REQ_MSCH0, 544 PMU_IDLE_REQ_MSCH1, 545 546 PMU_IDLE_REQ_ALIVE, 547 PMU_IDLE_REQ_PMU, 548 PMU_IDLE_REQ_EDP, 549 PMU_IDLE_REQ_GMAC, 550 551 PMU_IDLE_REQ_EMMC, 552 PMU_IDLE_REQ_CENTER1, 553 PMU_IDLE_REQ_PMUM0, 554 PMU_IDLE_REQ_GIC, 555 556 PMU_IDLE_REQ_SD, 557 PMU_IDLE_REQ_SDIOAUDIO, 558 }; 559 560 /* pmu bus idle status register */ 561 enum pmu_bus_idle_st { 562 PMU_IDLE_ST_GPU = 0, 563 PMU_IDLE_ST_PERILP, 564 PMU_IDLE_ST_PERIHP, 565 PMU_IDLE_ST_VCODEC, 566 567 PMU_IDLE_ST_VDU, 568 PMU_IDLE_ST_RGA, 569 PMU_IDLE_ST_IEP, 570 PMU_IDLE_ST_VOPB, 571 572 PMU_IDLE_ST_VOPL, 573 PMU_IDLE_ST_ISP0, 574 PMU_IDLE_ST_ISP1, 575 PMU_IDLE_ST_HDCP, 576 577 PMU_IDLE_ST_USB3, 578 PMU_IDLE_ST_PERILPM0, 579 PMU_IDLE_ST_CENTER, 580 PMU_IDLE_ST_CCIM0, 581 582 PMU_IDLE_ST_CCIM1, 583 PMU_IDLE_ST_VIO, 584 PMU_IDLE_ST_MSCH0, 585 PMU_IDLE_ST_MSCH1, 586 587 PMU_IDLE_ST_ALIVE, 588 PMU_IDLE_ST_PMU, 589 PMU_IDLE_ST_EDP, 590 PMU_IDLE_ST_GMAC, 591 592 PMU_IDLE_ST_EMMC, 593 PMU_IDLE_ST_CENTER1, 594 PMU_IDLE_ST_PMUM0, 595 PMU_IDLE_ST_GIC, 596 597 PMU_IDLE_ST_SD, 598 PMU_IDLE_ST_SDIOAUDIO, 599 }; 600 601 enum pmu_bus_idle_ack { 602 PMU_IDLE_ACK_GPU = 0, 603 PMU_IDLE_ACK_PERILP, 604 PMU_IDLE_ACK_PERIHP, 605 PMU_IDLE_ACK_VCODEC, 606 607 PMU_IDLE_ACK_VDU, 608 PMU_IDLE_ACK_RGA, 609 PMU_IDLE_ACK_IEP, 610 PMU_IDLE_ACK_VOPB, 611 612 PMU_IDLE_ACK_VOPL, 613 PMU_IDLE_ACK_ISP0, 614 PMU_IDLE_ACK_ISP1, 615 PMU_IDLE_ACK_HDCP, 616 617 PMU_IDLE_ACK_USB3, 618 PMU_IDLE_ACK_PERILPM0, 619 PMU_IDLE_ACK_CENTER, 620 PMU_IDLE_ACK_CCIM0, 621 622 PMU_IDLE_ACK_CCIM1, 623 PMU_IDLE_ACK_VIO, 624 PMU_IDLE_ACK_MSCH0, 625 PMU_IDLE_ACK_MSCH1, 626 627 PMU_IDLE_ACK_ALIVE, 628 PMU_IDLE_ACK_PMU, 629 PMU_IDLE_ACK_EDP, 630 PMU_IDLE_ACK_GMAC, 631 632 PMU_IDLE_ACK_EMMC, 633 PMU_IDLE_ACK_CENTER1, 634 PMU_IDLE_ACK_PMUM0, 635 PMU_IDLE_ACK_GIC, 636 637 PMU_IDLE_ACK_SD, 638 PMU_IDLE_ACK_SDIOAUDIO, 639 }; 640 641 enum pmu_pwrdn_con1 { 642 PMU_VD_SCU_L_PWRDN_EN = 0, 643 PMU_VD_SCU_B_PWRDN_EN, 644 PMU_VD_CENTER_PWRDN_EN, 645 }; 646 647 #define PMU_WKUP_CFG0 0x00 648 #define PMU_WKUP_CFG1 0x04 649 #define PMU_WKUP_CFG2 0x08 650 #define PMU_WKUP_CFG3 0x0c 651 #define PMU_WKUP_CFG4 0x10 652 #define PMU_PWRDN_CON 0x14 653 #define PMU_PWRDN_ST 0x18 654 #define PMU_PLL_CON 0x1c 655 #define PMU_PWRMODE_CON 0x20 656 #define PMU_SFT_CON 0x24 657 #define PMU_INT_CON 0x28 658 #define PMU_INT_ST 0x2c 659 #define PMU_GPIO0_POS_INT_CON 0x30 660 #define PMU_GPIO0_NEG_INT_CON 0x34 661 #define PMU_GPIO1_POS_INT_CON 0x38 662 #define PMU_GPIO1_NEG_INT_CON 0x3c 663 #define PMU_GPIO0_POS_INT_ST 0x40 664 #define PMU_GPIO0_NEG_INT_ST 0x44 665 #define PMU_GPIO1_POS_INT_ST 0x48 666 #define PMU_GPIO1_NEG_INT_ST 0x4c 667 #define PMU_PWRDN_INTEN 0x50 668 #define PMU_PWRDN_STATUS 0x54 669 #define PMU_WAKEUP_STATUS 0x58 670 #define PMU_BUS_CLR 0x5c 671 #define PMU_BUS_IDLE_REQ 0x60 672 #define PMU_BUS_IDLE_ST 0x64 673 #define PMU_BUS_IDLE_ACK 0x68 674 #define PMU_CCI500_CON 0x6c 675 #define PMU_ADB400_CON 0x70 676 #define PMU_ADB400_ST 0x74 677 #define PMU_POWER_ST 0x78 678 #define PMU_CORE_PWR_ST 0x7c 679 #define PMU_OSC_CNT 0x80 680 #define PMU_PLLLOCK_CNT 0x84 681 #define PMU_PLLRST_CNT 0x88 682 #define PMU_STABLE_CNT 0x8c 683 #define PMU_DDRIO_PWRON_CNT 0x90 684 #define PMU_WAKEUP_RST_CLR_CNT 0x94 685 #define PMU_DDR_SREF_ST 0x98 686 #define PMU_SCU_L_PWRDN_CNT 0x9c 687 #define PMU_SCU_L_PWRUP_CNT 0xa0 688 #define PMU_SCU_B_PWRDN_CNT 0xa4 689 #define PMU_SCU_B_PWRUP_CNT 0xa8 690 #define PMU_GPU_PWRDN_CNT 0xac 691 #define PMU_GPU_PWRUP_CNT 0xb0 692 #define PMU_CENTER_PWRDN_CNT 0xb4 693 #define PMU_CENTER_PWRUP_CNT 0xb8 694 #define PMU_TIMEOUT_CNT 0xbc 695 #define PMU_CPU0APM_CON 0xc0 696 #define PMU_CPU1APM_CON 0xc4 697 #define PMU_CPU2APM_CON 0xc8 698 #define PMU_CPU3APM_CON 0xcc 699 #define PMU_CPU0BPM_CON 0xd0 700 #define PMU_CPU1BPM_CON 0xd4 701 #define PMU_NOC_AUTO_ENA 0xd8 702 #define PMU_PWRDN_CON1 0xdc 703 704 #define CORES_PM_DISABLE 0x0 705 706 #define PD_CTR_LOOP 500 707 #define CHK_CPU_LOOP 500 708 709 #endif /* __PMU_H__ */ 710