1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_H__ 32 #define __PMU_H__ 33 34 /* Allocate sp reginon in pmusram */ 35 #define PSRAM_SP_SIZE 0x80 36 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 37 38 /***************************************************************************** 39 * Common define for per soc pmu.h 40 *****************************************************************************/ 41 /* The ways of cores power domain contorlling */ 42 enum cores_pm_ctr_mode { 43 core_pwr_pd = 0, 44 core_pwr_wfi = 1, 45 core_pwr_wfi_int = 2 46 }; 47 48 /***************************************************************************** 49 * pmu con,reg 50 *****************************************************************************/ 51 #define PMU_WKUP_CFG(n) ((n) * 4) 52 53 #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) 54 55 /* the shift of bits for cores status */ 56 enum pmu_core_pwrst_shift { 57 clstl_cpu_wfe = 2, 58 clstl_cpu_wfi = 6, 59 clstb_cpu_wfe = 12, 60 clstb_cpu_wfi = 16 61 }; 62 63 #define CKECK_WFE_MSK 0x1 64 #define CKECK_WFI_MSK 0x10 65 #define CKECK_WFEI_MSK 0x11 66 67 enum pmu_powerdomain_id { 68 PD_CPUL0 = 0, 69 PD_CPUL1, 70 PD_CPUL2, 71 PD_CPUL3, 72 PD_CPUB0, 73 PD_CPUB1, 74 PD_SCUL, 75 PD_SCUB, 76 PD_TCPD0, 77 PD_TCPD1, 78 PD_CCI, 79 PD_PERILP, 80 PD_PERIHP, 81 PD_CENTER, 82 PD_VIO, 83 PD_GPU, 84 PD_VCODEC, 85 PD_VDU, 86 PD_RGA, 87 PD_IEP, 88 PD_VO, 89 PD_ISP0 = 22, 90 PD_ISP1, 91 PD_HDCP, 92 PD_GMAC, 93 PD_EMMC, 94 PD_USB3, 95 PD_EDP, 96 PD_GIC, 97 PD_SD, 98 PD_SDIOAUDIO, 99 PD_END 100 }; 101 102 enum powerdomain_state { 103 PMU_POWER_ON = 0, 104 PMU_POWER_OFF, 105 }; 106 107 enum pmu_bus_id { 108 BUS_ID_GPU = 0, 109 BUS_ID_PERILP, 110 BUS_ID_PERIHP, 111 BUS_ID_VCODEC, 112 BUS_ID_VDU, 113 BUS_ID_RGA, 114 BUS_ID_IEP, 115 BUS_ID_VOPB, 116 BUS_ID_VOPL, 117 BUS_ID_ISP0, 118 BUS_ID_ISP1, 119 BUS_ID_HDCP, 120 BUS_ID_USB3, 121 BUS_ID_PERILPM0, 122 BUS_ID_CENTER, 123 BUS_ID_CCIM0, 124 BUS_ID_CCIM1, 125 BUS_ID_VIO, 126 BUS_ID_MSCH0, 127 BUS_ID_MSCH1, 128 BUS_ID_ALIVE, 129 BUS_ID_PMU, 130 BUS_ID_EDP, 131 BUS_ID_GMAC, 132 BUS_ID_EMMC, 133 BUS_ID_CENTER1, 134 BUS_ID_PMUM0, 135 BUS_ID_GIC, 136 BUS_ID_SD, 137 BUS_ID_SDIOAUDIO, 138 }; 139 140 enum pmu_bus_state { 141 BUS_ACTIVE, 142 BUS_IDLE, 143 }; 144 145 /* pmu_cpuapm bit */ 146 enum pmu_cores_pm_by_wfi { 147 core_pm_en = 0, 148 core_pm_int_wakeup_en, 149 core_pm_resv, 150 core_pm_sft_wakeup_en 151 }; 152 153 enum pmu_wkup_cfg0 { 154 PMU_GPIO0A_POSE_WKUP_EN = 0, 155 PMU_GPIO0B_POSE_WKUP_EN = 8, 156 PMU_GPIO0C_POSE_WKUP_EN = 16, 157 PMU_GPIO0D_POSE_WKUP_EN = 24, 158 }; 159 160 enum pmu_wkup_cfg1 { 161 PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, 162 PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, 163 PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, 164 PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, 165 }; 166 167 enum pmu_wkup_cfg2 { 168 PMU_GPIO1A_POSE_WKUP_EN = 0, 169 PMU_GPIO1B_POSE_WKUP_EN = 7, 170 PMU_GPIO1C_POSE_WKUP_EN = 16, 171 PMU_GPIO1D_POSE_WKUP_EN = 24, 172 }; 173 174 enum pmu_wkup_cfg3 { 175 PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, 176 PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, 177 PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, 178 PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, 179 }; 180 181 /* pmu_wkup_cfg4 */ 182 enum pmu_wkup_cfg4 { 183 PMU_CLUSTER_L_WKUP_EN = 0, 184 PMU_CLUSTER_B_WKUP_EN, 185 PMU_GPIO_WKUP_EN, 186 PMU_SDIO_WKUP_EN, 187 188 PMU_SDMMC_WKUP_EN, 189 PMU_TIMER_WKUP_EN = 6, 190 PMU_USBDEV_WKUP_EN, 191 192 PMU_SFT_WKUP_EN, 193 PMU_M0_WDT_WKUP_EN, 194 PMU_TIMEOUT_WKUP_EN, 195 PMU_PWM_WKUP_EN, 196 197 PMU_PCIE_WKUP_EN = 13, 198 }; 199 200 enum pmu_pwrdn_con { 201 PMU_A53_L0_PWRDWN_EN = 0, 202 PMU_A53_L1_PWRDWN_EN, 203 PMU_A53_L2_PWRDWN_EN, 204 PMU_A53_L3_PWRDWN_EN, 205 206 PMU_A72_B0_PWRDWN_EN, 207 PMU_A72_B1_PWRDWN_EN, 208 PMU_SCU_L_PWRDWN_EN, 209 PMU_SCU_B_PWRDWN_EN, 210 211 PMU_TCPD0_PWRDWN_EN, 212 PMU_TCPD1_PWRDWN_EN, 213 PMU_CCI_PWRDWN_EN, 214 PMU_PERILP_PWRDWN_EN, 215 216 PMU_PERIHP_PWRDWN_EN, 217 PMU_CENTER_PWRDWN_EN, 218 PMU_VIO_PWRDWN_EN, 219 PMU_GPU_PWRDWN_EN, 220 221 PMU_VCODEC_PWRDWN_EN, 222 PMU_VDU_PWRDWN_EN, 223 PMU_RGA_PWRDWN_EN, 224 PMU_IEP_PWRDWN_EN, 225 226 PMU_VO_PWRDWN_EN, 227 PMU_ISP0_PWRDWN_EN = 22, 228 PMU_ISP1_PWRDWN_EN, 229 230 PMU_HDCP_PWRDWN_EN, 231 PMU_GMAC_PWRDWN_EN, 232 PMU_EMMC_PWRDWN_EN, 233 PMU_USB3_PWRDWN_EN, 234 235 PMU_EDP_PWRDWN_EN, 236 PMU_GIC_PWRDWN_EN, 237 PMU_SD_PWRDWN_EN, 238 PMU_SDIOAUDIO_PWRDWN_EN, 239 }; 240 241 enum pmu_pwrdn_st { 242 PMU_A53_L0_PWRDWN_ST = 0, 243 PMU_A53_L1_PWRDWN_ST, 244 PMU_A53_L2_PWRDWN_ST, 245 PMU_A53_L3_PWRDWN_ST, 246 247 PMU_A72_B0_PWRDWN_ST, 248 PMU_A72_B1_PWRDWN_ST, 249 PMU_SCU_L_PWRDWN_ST, 250 PMU_SCU_B_PWRDWN_ST, 251 252 PMU_TCPD0_PWRDWN_ST, 253 PMU_TCPD1_PWRDWN_ST, 254 PMU_CCI_PWRDWN_ST, 255 PMU_PERILP_PWRDWN_ST, 256 257 PMU_PERIHP_PWRDWN_ST, 258 PMU_CENTER_PWRDWN_ST, 259 PMU_VIO_PWRDWN_ST, 260 PMU_GPU_PWRDWN_ST, 261 262 PMU_VCODEC_PWRDWN_ST, 263 PMU_VDU_PWRDWN_ST, 264 PMU_RGA_PWRDWN_ST, 265 PMU_IEP_PWRDWN_ST, 266 267 PMU_VO_PWRDWN_ST, 268 PMU_ISP0_PWRDWN_ST = 22, 269 PMU_ISP1_PWRDWN_ST, 270 271 PMU_HDCP_PWRDWN_ST, 272 PMU_GMAC_PWRDWN_ST, 273 PMU_EMMC_PWRDWN_ST, 274 PMU_USB3_PWRDWN_ST, 275 276 PMU_EDP_PWRDWN_ST, 277 PMU_GIC_PWRDWN_ST, 278 PMU_SD_PWRDWN_ST, 279 PMU_SDIOAUDIO_PWRDWN_ST, 280 281 }; 282 283 enum pmu_pll_con { 284 PMU_PLL_PD_CFG = 0, 285 PMU_SFT_PLL_PD = 8, 286 }; 287 288 enum pmu_pwermode_con { 289 PMU_PWR_MODE_EN = 0, 290 PMU_WKUP_RST_EN, 291 PMU_INPUT_CLAMP_EN, 292 PMU_OSC_DIS, 293 294 PMU_ALIVE_USE_LF, 295 PMU_PMU_USE_LF, 296 PMU_POWER_OFF_REQ_CFG, 297 PMU_CHIP_PD_EN, 298 299 PMU_PLL_PD_EN, 300 PMU_CPU0_PD_EN, 301 PMU_L2_FLUSH_EN, 302 PMU_L2_IDLE_EN, 303 304 PMU_SCU_PD_EN, 305 PMU_CCI_PD_EN, 306 PMU_PERILP_PD_EN, 307 PMU_CENTER_PD_EN, 308 309 PMU_SREF0_ENTER_EN, 310 PMU_DDRC0_GATING_EN, 311 PMU_DDRIO0_RET_EN, 312 PMU_DDRIO0_RET_DE_REQ, 313 314 PMU_SREF1_ENTER_EN, 315 PMU_DDRC1_GATING_EN, 316 PMU_DDRIO1_RET_EN, 317 PMU_DDRIO1_RET_DE_REQ, 318 319 PMU_CLK_CENTER_SRC_GATE_EN = 26, 320 PMU_CLK_PERILP_SRC_GATE_EN, 321 322 PMU_CLK_CORE_SRC_GATE_EN, 323 PMU_DDRIO_RET_HW_DE_REQ, 324 PMU_SLP_OUTPUT_CFG, 325 PMU_MAIN_CLUSTER, 326 }; 327 328 enum pmu_sft_con { 329 PMU_WKUP_SFT = 0, 330 PMU_INPUT_CLAMP_CFG, 331 PMU_OSC_DIS_CFG, 332 PMU_PMU_LF_EN_CFG, 333 334 PMU_ALIVE_LF_EN_CFG, 335 PMU_24M_EN_CFG, 336 PMU_DBG_PWRUP_L0_CFG, 337 PMU_WKUP_SFT_M0, 338 339 PMU_DDRCTL0_C_SYSREQ_CFG, 340 PMU_DDR0_IO_RET_CFG, 341 342 PMU_DDRCTL1_C_SYSREQ_CFG = 12, 343 PMU_DDR1_IO_RET_CFG, 344 DBG_PWRUP_B0_CFG = 15, 345 346 DBG_NOPWERDWN_L0_EN, 347 DBG_NOPWERDWN_L1_EN, 348 DBG_NOPWERDWN_L2_EN, 349 DBG_NOPWERDWN_L3_EN, 350 351 DBG_PWRUP_REQ_L_EN = 20, 352 CLUSTER_L_CLK_SRC_GATING_CFG, 353 L2_FLUSH_REQ_CLUSTER_L, 354 ACINACTM_CLUSTER_L_CFG, 355 356 DBG_NO_PWERDWN_B0_EN, 357 DBG_NO_PWERDWN_B1_EN, 358 359 DBG_PWRUP_REQ_B_EN = 28, 360 CLUSTER_B_CLK_SRC_GATING_CFG, 361 L2_FLUSH_REQ_CLUSTER_B, 362 ACINACTM_CLUSTER_B_CFG, 363 }; 364 365 enum pmu_int_con { 366 PMU_PMU_INT_EN = 0, 367 PMU_PWRMD_WKUP_INT_EN, 368 PMU_WKUP_GPIO0_NEG_INT_EN, 369 PMU_WKUP_GPIO0_POS_INT_EN, 370 PMU_WKUP_GPIO1_NEG_INT_EN, 371 PMU_WKUP_GPIO1_POS_INT_EN, 372 }; 373 374 enum pmu_int_st { 375 PMU_PWRMD_WKUP_INT_ST = 1, 376 PMU_WKUP_GPIO0_NEG_INT_ST, 377 PMU_WKUP_GPIO0_POS_INT_ST, 378 PMU_WKUP_GPIO1_NEG_INT_ST, 379 PMU_WKUP_GPIO1_POS_INT_ST, 380 }; 381 382 enum pmu_gpio0_pos_int_con { 383 PMU_GPIO0A_POS_INT_EN = 0, 384 PMU_GPIO0B_POS_INT_EN = 8, 385 PMU_GPIO0C_POS_INT_EN = 16, 386 PMU_GPIO0D_POS_INT_EN = 24, 387 }; 388 389 enum pmu_gpio0_neg_int_con { 390 PMU_GPIO0A_NEG_INT_EN = 0, 391 PMU_GPIO0B_NEG_INT_EN = 8, 392 PMU_GPIO0C_NEG_INT_EN = 16, 393 PMU_GPIO0D_NEG_INT_EN = 24, 394 }; 395 396 enum pmu_gpio1_pos_int_con { 397 PMU_GPIO1A_POS_INT_EN = 0, 398 PMU_GPIO1B_POS_INT_EN = 8, 399 PMU_GPIO1C_POS_INT_EN = 16, 400 PMU_GPIO1D_POS_INT_EN = 24, 401 }; 402 403 enum pmu_gpio1_neg_int_con { 404 PMU_GPIO1A_NEG_INT_EN = 0, 405 PMU_GPIO1B_NEG_INT_EN = 8, 406 PMU_GPIO1C_NEG_INT_EN = 16, 407 PMU_GPIO1D_NEG_INT_EN = 24, 408 }; 409 410 enum pmu_gpio0_pos_int_st { 411 PMU_GPIO0A_POS_INT_ST = 0, 412 PMU_GPIO0B_POS_INT_ST = 8, 413 PMU_GPIO0C_POS_INT_ST = 16, 414 PMU_GPIO0D_POS_INT_ST = 24, 415 }; 416 417 enum pmu_gpio0_neg_int_st { 418 PMU_GPIO0A_NEG_INT_ST = 0, 419 PMU_GPIO0B_NEG_INT_ST = 8, 420 PMU_GPIO0C_NEG_INT_ST = 16, 421 PMU_GPIO0D_NEG_INT_ST = 24, 422 }; 423 424 enum pmu_gpio1_pos_int_st { 425 PMU_GPIO1A_POS_INT_ST = 0, 426 PMU_GPIO1B_POS_INT_ST = 8, 427 PMU_GPIO1C_POS_INT_ST = 16, 428 PMU_GPIO1D_POS_INT_ST = 24, 429 }; 430 431 enum pmu_gpio1_neg_int_st { 432 PMU_GPIO1A_NEG_INT_ST = 0, 433 PMU_GPIO1B_NEG_INT_ST = 8, 434 PMU_GPIO1C_NEG_INT_ST = 16, 435 PMU_GPIO1D_NEG_INT_ST = 24, 436 }; 437 438 /* pmu power down configure register 0x0050 */ 439 enum pmu_pwrdn_inten { 440 PMU_A53_L0_PWR_SWITCH_INT_EN = 0, 441 PMU_A53_L1_PWR_SWITCH_INT_EN, 442 PMU_A53_L2_PWR_SWITCH_INT_EN, 443 PMU_A53_L3_PWR_SWITCH_INT_EN, 444 445 PMU_A72_B0_PWR_SWITCH_INT_EN, 446 PMU_A72_B1_PWR_SWITCH_INT_EN, 447 PMU_SCU_L_PWR_SWITCH_INT_EN, 448 PMU_SCU_B_PWR_SWITCH_INT_EN, 449 450 PMU_TCPD0_PWR_SWITCH_INT_EN, 451 PMU_TCPD1_PWR_SWITCH_INT_EN, 452 PMU_CCI_PWR_SWITCH_INT_EN, 453 PMU_PERILP_PWR_SWITCH_INT_EN, 454 455 PMU_PERIHP_PWR_SWITCH_INT_EN, 456 PMU_CENTER_PWR_SWITCH_INT_EN, 457 PMU_VIO_PWR_SWITCH_INT_EN, 458 PMU_GPU_PWR_SWITCH_INT_EN, 459 460 PMU_VCODEC_PWR_SWITCH_INT_EN, 461 PMU_VDU_PWR_SWITCH_INT_EN, 462 PMU_RGA_PWR_SWITCH_INT_EN, 463 PMU_IEP_PWR_SWITCH_INT_EN, 464 465 PMU_VO_PWR_SWITCH_INT_EN, 466 PMU_ISP0_PWR_SWITCH_INT_EN = 22, 467 PMU_ISP1_PWR_SWITCH_INT_EN, 468 469 PMU_HDCP_PWR_SWITCH_INT_EN, 470 PMU_GMAC_PWR_SWITCH_INT_EN, 471 PMU_EMMC_PWR_SWITCH_INT_EN, 472 PMU_USB3_PWR_SWITCH_INT_EN, 473 474 PMU_EDP_PWR_SWITCH_INT_EN, 475 PMU_GIC_PWR_SWITCH_INT_EN, 476 PMU_SD_PWR_SWITCH_INT_EN, 477 PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, 478 }; 479 480 enum pmu_wkup_status { 481 PMU_WKUP_BY_CLSTER_L_INT = 0, 482 PMU_WKUP_BY_CLSTER_b_INT, 483 PMU_WKUP_BY_GPIO_INT, 484 PMU_WKUP_BY_SDIO_DET, 485 486 PMU_WKUP_BY_SDMMC_DET, 487 PMU_WKUP_BY_TIMER = 6, 488 PMU_WKUP_BY_USBDEV_DET, 489 490 PMU_WKUP_BY_M0_SFT, 491 PMU_WKUP_BY_M0_WDT_INT, 492 PMU_WKUP_BY_TIMEOUT, 493 PMU_WKUP_BY_PWM, 494 495 PMU_WKUP_BY_PCIE = 13, 496 }; 497 498 enum pmu_bus_clr { 499 PMU_CLR_GPU = 0, 500 PMU_CLR_PERILP, 501 PMU_CLR_PERIHP, 502 PMU_CLR_VCODEC, 503 504 PMU_CLR_VDU, 505 PMU_CLR_RGA, 506 PMU_CLR_IEP, 507 PMU_CLR_VOPB, 508 509 PMU_CLR_VOPL, 510 PMU_CLR_ISP0, 511 PMU_CLR_ISP1, 512 PMU_CLR_HDCP, 513 514 PMU_CLR_USB3, 515 PMU_CLR_PERILPM0, 516 PMU_CLR_CENTER, 517 PMU_CLR_CCIM1, 518 519 PMU_CLR_CCIM0, 520 PMU_CLR_VIO, 521 PMU_CLR_MSCH0, 522 PMU_CLR_MSCH1, 523 524 PMU_CLR_ALIVE, 525 PMU_CLR_PMU, 526 PMU_CLR_EDP, 527 PMU_CLR_GMAC, 528 529 PMU_CLR_EMMC, 530 PMU_CLR_CENTER1, 531 PMU_CLR_PMUM0, 532 PMU_CLR_GIC, 533 534 PMU_CLR_SD, 535 PMU_CLR_SDIOAUDIO, 536 }; 537 538 /* PMU bus idle request register */ 539 enum pmu_bus_idle_req { 540 PMU_IDLE_REQ_GPU = 0, 541 PMU_IDLE_REQ_PERILP, 542 PMU_IDLE_REQ_PERIHP, 543 PMU_IDLE_REQ_VCODEC, 544 545 PMU_IDLE_REQ_VDU, 546 PMU_IDLE_REQ_RGA, 547 PMU_IDLE_REQ_IEP, 548 PMU_IDLE_REQ_VOPB, 549 550 PMU_IDLE_REQ_VOPL, 551 PMU_IDLE_REQ_ISP0, 552 PMU_IDLE_REQ_ISP1, 553 PMU_IDLE_REQ_HDCP, 554 555 PMU_IDLE_REQ_USB3, 556 PMU_IDLE_REQ_PERILPM0, 557 PMU_IDLE_REQ_CENTER, 558 PMU_IDLE_REQ_CCIM0, 559 560 PMU_IDLE_REQ_CCIM1, 561 PMU_IDLE_REQ_VIO, 562 PMU_IDLE_REQ_MSCH0, 563 PMU_IDLE_REQ_MSCH1, 564 565 PMU_IDLE_REQ_ALIVE, 566 PMU_IDLE_REQ_PMU, 567 PMU_IDLE_REQ_EDP, 568 PMU_IDLE_REQ_GMAC, 569 570 PMU_IDLE_REQ_EMMC, 571 PMU_IDLE_REQ_CENTER1, 572 PMU_IDLE_REQ_PMUM0, 573 PMU_IDLE_REQ_GIC, 574 575 PMU_IDLE_REQ_SD, 576 PMU_IDLE_REQ_SDIOAUDIO, 577 }; 578 579 /* pmu bus idle status register */ 580 enum pmu_bus_idle_st { 581 PMU_IDLE_ST_GPU = 0, 582 PMU_IDLE_ST_PERILP, 583 PMU_IDLE_ST_PERIHP, 584 PMU_IDLE_ST_VCODEC, 585 586 PMU_IDLE_ST_VDU, 587 PMU_IDLE_ST_RGA, 588 PMU_IDLE_ST_IEP, 589 PMU_IDLE_ST_VOPB, 590 591 PMU_IDLE_ST_VOPL, 592 PMU_IDLE_ST_ISP0, 593 PMU_IDLE_ST_ISP1, 594 PMU_IDLE_ST_HDCP, 595 596 PMU_IDLE_ST_USB3, 597 PMU_IDLE_ST_PERILPM0, 598 PMU_IDLE_ST_CENTER, 599 PMU_IDLE_ST_CCIM0, 600 601 PMU_IDLE_ST_CCIM1, 602 PMU_IDLE_ST_VIO, 603 PMU_IDLE_ST_MSCH0, 604 PMU_IDLE_ST_MSCH1, 605 606 PMU_IDLE_ST_ALIVE, 607 PMU_IDLE_ST_PMU, 608 PMU_IDLE_ST_EDP, 609 PMU_IDLE_ST_GMAC, 610 611 PMU_IDLE_ST_EMMC, 612 PMU_IDLE_ST_CENTER1, 613 PMU_IDLE_ST_PMUM0, 614 PMU_IDLE_ST_GIC, 615 616 PMU_IDLE_ST_SD, 617 PMU_IDLE_ST_SDIOAUDIO, 618 }; 619 620 enum pmu_bus_idle_ack { 621 PMU_IDLE_ACK_GPU = 0, 622 PMU_IDLE_ACK_PERILP, 623 PMU_IDLE_ACK_PERIHP, 624 PMU_IDLE_ACK_VCODEC, 625 626 PMU_IDLE_ACK_VDU, 627 PMU_IDLE_ACK_RGA, 628 PMU_IDLE_ACK_IEP, 629 PMU_IDLE_ACK_VOPB, 630 631 PMU_IDLE_ACK_VOPL, 632 PMU_IDLE_ACK_ISP0, 633 PMU_IDLE_ACK_ISP1, 634 PMU_IDLE_ACK_HDCP, 635 636 PMU_IDLE_ACK_USB3, 637 PMU_IDLE_ACK_PERILPM0, 638 PMU_IDLE_ACK_CENTER, 639 PMU_IDLE_ACK_CCIM0, 640 641 PMU_IDLE_ACK_CCIM1, 642 PMU_IDLE_ACK_VIO, 643 PMU_IDLE_ACK_MSCH0, 644 PMU_IDLE_ACK_MSCH1, 645 646 PMU_IDLE_ACK_ALIVE, 647 PMU_IDLE_ACK_PMU, 648 PMU_IDLE_ACK_EDP, 649 PMU_IDLE_ACK_GMAC, 650 651 PMU_IDLE_ACK_EMMC, 652 PMU_IDLE_ACK_CENTER1, 653 PMU_IDLE_ACK_PMUM0, 654 PMU_IDLE_ACK_GIC, 655 656 PMU_IDLE_ACK_SD, 657 PMU_IDLE_ACK_SDIOAUDIO, 658 }; 659 660 enum pmu_cci500_con { 661 PMU_PREQ_CCI500_CFG_SW = 0, 662 PMU_CLR_PREQ_CCI500_HW, 663 PMU_PSTATE_CCI500_0, 664 PMU_PSTATE_CCI500_1, 665 666 PMU_PSTATE_CCI500_2, 667 PMU_QREQ_CCI500_CFG_SW, 668 PMU_CLR_QREQ_CCI500_HW, 669 PMU_QGATING_CCI500_CFG, 670 671 PMU_PREQ_CCI500_CFG_SW_WMSK = 16, 672 PMU_CLR_PREQ_CCI500_HW_WMSK, 673 PMU_PSTATE_CCI500_0_WMSK, 674 PMU_PSTATE_CCI500_1_WMSK, 675 676 PMU_PSTATE_CCI500_2_WMSK, 677 PMU_QREQ_CCI500_CFG_SW_WMSK, 678 PMU_CLR_QREQ_CCI500_HW_WMSK, 679 PMU_QGATING_CCI500_CFG_WMSK, 680 }; 681 682 enum pmu_adb400_con { 683 PMU_PWRDWN_REQ_CXCS_SW = 0, 684 PMU_PWRDWN_REQ_CORE_L_SW, 685 PMU_PWRDWN_REQ_CORE_L_2GIC_SW, 686 PMU_PWRDWN_REQ_GIC2_CORE_L_SW, 687 688 PMU_PWRDWN_REQ_CORE_B_SW, 689 PMU_PWRDWN_REQ_CORE_B_2GIC_SW, 690 PMU_PWRDWN_REQ_GIC2_CORE_B_SW, 691 692 PMU_CLR_CXCS_HW = 8, 693 PMU_CLR_CORE_L_HW, 694 PMU_CLR_CORE_L_2GIC_HW, 695 PMU_CLR_GIC2_CORE_L_HW, 696 697 PMU_CLR_CORE_B_HW, 698 PMU_CLR_CORE_B_2GIC_HW, 699 PMU_CLR_GIC2_CORE_B_HW, 700 701 PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, 702 PMU_PWRDWN_REQ_CORE_L_SW_WMSK, 703 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, 704 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, 705 706 PMU_PWRDWN_REQ_CORE_B_SW_WMSK, 707 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, 708 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, 709 710 PMU_CLR_CXCS_HW_WMSK = 24, 711 PMU_CLR_CORE_L_HW_WMSK, 712 PMU_CLR_CORE_L_2GIC_HW_WMSK, 713 PMU_CLR_GIC2_CORE_L_HW_WMSK, 714 715 PMU_CLR_CORE_B_HW_WMSK, 716 PMU_CLR_CORE_B_2GIC_HW_WMSK, 717 PMU_CLR_GIC2_CORE_B_HW_WMSK, 718 }; 719 720 enum pmu_adb400_st { 721 PMU_PWRDWN_REQ_CXCS_SW_ST = 0, 722 PMU_PWRDWN_REQ_CORE_L_SW_ST, 723 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, 724 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, 725 726 PMU_PWRDWN_REQ_CORE_B_SW_ST, 727 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, 728 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, 729 730 PMU_CLR_CXCS_HW_ST = 8, 731 PMU_CLR_CORE_L_HW_ST, 732 PMU_CLR_CORE_L_2GIC_HW_ST, 733 PMU_CLR_GIC2_CORE_L_HW_ST, 734 735 PMU_CLR_CORE_B_HW_ST, 736 PMU_CLR_CORE_B_2GIC_HW_ST, 737 PMU_CLR_GIC2_CORE_B_HW_ST, 738 }; 739 740 enum pmu_pwrdn_con1 { 741 PMU_VD_SCU_L_PWRDN_EN = 0, 742 PMU_VD_SCU_B_PWRDN_EN, 743 PMU_VD_CENTER_PWRDN_EN, 744 }; 745 746 enum pmu_core_pwr_st { 747 L2_FLUSHDONE_CLUSTER_L = 0, 748 STANDBY_BY_WFIL2_CLUSTER_L, 749 750 L2_FLUSHDONE_CLUSTER_B = 10, 751 STANDBY_BY_WFIL2_CLUSTER_B, 752 }; 753 754 #define PMU_WKUP_CFG0 0x00 755 #define PMU_WKUP_CFG1 0x04 756 #define PMU_WKUP_CFG2 0x08 757 #define PMU_WKUP_CFG3 0x0c 758 #define PMU_WKUP_CFG4 0x10 759 #define PMU_PWRDN_CON 0x14 760 #define PMU_PWRDN_ST 0x18 761 #define PMU_PLL_CON 0x1c 762 #define PMU_PWRMODE_CON 0x20 763 #define PMU_SFT_CON 0x24 764 #define PMU_INT_CON 0x28 765 #define PMU_INT_ST 0x2c 766 #define PMU_GPIO0_POS_INT_CON 0x30 767 #define PMU_GPIO0_NEG_INT_CON 0x34 768 #define PMU_GPIO1_POS_INT_CON 0x38 769 #define PMU_GPIO1_NEG_INT_CON 0x3c 770 #define PMU_GPIO0_POS_INT_ST 0x40 771 #define PMU_GPIO0_NEG_INT_ST 0x44 772 #define PMU_GPIO1_POS_INT_ST 0x48 773 #define PMU_GPIO1_NEG_INT_ST 0x4c 774 #define PMU_PWRDN_INTEN 0x50 775 #define PMU_PWRDN_STATUS 0x54 776 #define PMU_WAKEUP_STATUS 0x58 777 #define PMU_BUS_CLR 0x5c 778 #define PMU_BUS_IDLE_REQ 0x60 779 #define PMU_BUS_IDLE_ST 0x64 780 #define PMU_BUS_IDLE_ACK 0x68 781 #define PMU_CCI500_CON 0x6c 782 #define PMU_ADB400_CON 0x70 783 #define PMU_ADB400_ST 0x74 784 #define PMU_POWER_ST 0x78 785 #define PMU_CORE_PWR_ST 0x7c 786 #define PMU_OSC_CNT 0x80 787 #define PMU_PLLLOCK_CNT 0x84 788 #define PMU_PLLRST_CNT 0x88 789 #define PMU_STABLE_CNT 0x8c 790 #define PMU_DDRIO_PWRON_CNT 0x90 791 #define PMU_WAKEUP_RST_CLR_CNT 0x94 792 #define PMU_DDR_SREF_ST 0x98 793 #define PMU_SCU_L_PWRDN_CNT 0x9c 794 #define PMU_SCU_L_PWRUP_CNT 0xa0 795 #define PMU_SCU_B_PWRDN_CNT 0xa4 796 #define PMU_SCU_B_PWRUP_CNT 0xa8 797 #define PMU_GPU_PWRDN_CNT 0xac 798 #define PMU_GPU_PWRUP_CNT 0xb0 799 #define PMU_CENTER_PWRDN_CNT 0xb4 800 #define PMU_CENTER_PWRUP_CNT 0xb8 801 #define PMU_TIMEOUT_CNT 0xbc 802 #define PMU_CPU0APM_CON 0xc0 803 #define PMU_CPU1APM_CON 0xc4 804 #define PMU_CPU2APM_CON 0xc8 805 #define PMU_CPU3APM_CON 0xcc 806 #define PMU_CPU0BPM_CON 0xd0 807 #define PMU_CPU1BPM_CON 0xd4 808 #define PMU_NOC_AUTO_ENA 0xd8 809 #define PMU_PWRDN_CON1 0xdc 810 811 #define PMUGRF_GPIO0A_IOMUX 0x00 812 #define PMUGRF_GPIO1A_IOMUX 0x10 813 #define AP_PWROFF 0x0a 814 #define GPIO0A6_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 12) 815 #define GPIO0A6_IOMUX_PWM BITS_WITH_WMASK(1, 3, 12) 816 #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) 817 #define TSADC_INT_PIN 38 818 #define CORES_PM_DISABLE 0x0 819 #define CPU_AXI_QOS_ID_COREID 0x00 820 #define CPU_AXI_QOS_REVISIONID 0x04 821 #define CPU_AXI_QOS_PRIORITY 0x08 822 #define CPU_AXI_QOS_MODE 0x0c 823 #define CPU_AXI_QOS_BANDWIDTH 0x10 824 #define CPU_AXI_QOS_SATURATION 0x14 825 #define CPU_AXI_QOS_EXTCONTROL 0x18 826 #define CPU_AXI_QOS_NUM_REGS 0x07 827 828 #define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000 829 #define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000 830 #define CPU_AXI_DMAC0_QOS_BASE 0xffa64200 831 #define CPU_AXI_DMAC1_QOS_BASE 0xffa64280 832 #define CPU_AXI_DCF_QOS_BASE 0xffa64180 833 #define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100 834 #define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080 835 #define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000 836 #define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300 837 #define CPU_AXI_GIC_QOS_BASE 0xffa78000 838 #define CPU_AXI_SDIO_QOS_BASE 0xffa76000 839 #define CPU_AXI_SDMMC_QOS_BASE 0xffa74000 840 #define CPU_AXI_EMMC_QOS_BASE 0xffa58000 841 #define CPU_AXI_GMAC_QOS_BASE 0xffa5c000 842 #define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000 843 #define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080 844 #define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100 845 #define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180 846 #define CPU_AXI_GPU_QOS_BASE 0xffae0000 847 #define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000 848 #define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000 849 #define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080 850 #define CPU_AXI_RGA_R_QOS_BASE 0xffab0000 851 #define CPU_AXI_RGA_W_QOS_BASE 0xffab0080 852 #define CPU_AXI_IEP_QOS_BASE 0xffa98000 853 #define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000 854 #define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080 855 #define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000 856 #define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000 857 #define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080 858 #define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000 859 #define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080 860 #define CPU_AXI_HDCP_QOS_BASE 0xffa90000 861 #define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080 862 #define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180 863 #define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100 864 865 #define PD_CTR_LOOP 500 866 #define CHK_CPU_LOOP 500 867 #define MAX_WAIT_COUNT 1000 868 869 #define GRF_SOC_CON4 0x0e210 870 #define PMUGRF_SOC_CON0 0x0180 871 872 #define CCI_FORCE_WAKEUP WMSK_BIT(8) 873 #define EXTERNAL_32K WMSK_BIT(0) 874 875 #define PLL_PD_HW 0xff 876 #define IOMUX_CLK_32K 0x00030002 877 #define NOC_AUTO_ENABLE 0x3fffffff 878 879 #define SAVE_QOS(array, NAME) \ 880 RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 881 #define RESTORE_QOS(array, NAME) \ 882 RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 883 884 #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ 885 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ 886 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ 887 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ 888 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ 889 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ 890 array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ 891 array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ 892 } while (0) 893 894 #define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ 895 mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ 896 mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ 897 mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ 898 mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ 899 mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ 900 mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ 901 mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ 902 } while (0) 903 904 struct pmu_slpdata_s { 905 uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; 906 uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; 907 uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; 908 uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; 909 uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; 910 uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; 911 uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; 912 uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; 913 uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; 914 uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; 915 uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; 916 uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; 917 uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; 918 uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; 919 uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; 920 uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; 921 uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; 922 uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; 923 uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; 924 uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; 925 uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; 926 uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; 927 uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; 928 uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; 929 uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; 930 uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; 931 uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; 932 uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; 933 uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; 934 uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; 935 uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; 936 uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; 937 uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 938 uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 939 uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 940 uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; 941 }; 942 943 extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; 944 #endif /* __PMU_H__ */ 945