1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_H__ 32 #define __PMU_H__ 33 34 #include <pmu_bits.h> 35 #include <pmu_regs.h> 36 #include <soc.h> 37 38 /* Allocate sp reginon in pmusram */ 39 #define PSRAM_SP_SIZE 0x80 40 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 41 42 /***************************************************************************** 43 * Common define for per soc pmu.h 44 *****************************************************************************/ 45 /* The ways of cores power domain contorlling */ 46 enum cores_pm_ctr_mode { 47 core_pwr_pd = 0, 48 core_pwr_wfi = 1, 49 core_pwr_wfi_int = 2 50 }; 51 52 /***************************************************************************** 53 * pmu con,reg 54 *****************************************************************************/ 55 #define PMU_WKUP_CFG(n) ((n) * 4) 56 57 #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) 58 59 /* the shift of bits for cores status */ 60 enum pmu_core_pwrst_shift { 61 clstl_cpu_wfe = 2, 62 clstl_cpu_wfi = 6, 63 clstb_cpu_wfe = 12, 64 clstb_cpu_wfi = 16 65 }; 66 67 #define CKECK_WFE_MSK 0x1 68 #define CKECK_WFI_MSK 0x10 69 #define CKECK_WFEI_MSK 0x11 70 71 /* Specific features required */ 72 #define AP_PWROFF 0x0a 73 74 #define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) 75 #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) 76 77 #define TSADC_INT_PIN 38 78 #define CORES_PM_DISABLE 0x0 79 80 #define PD_CTR_LOOP 500 81 #define CHK_CPU_LOOP 500 82 #define MAX_WAIT_COUNT 1000 83 84 #define GRF_SOC_CON4 0x0e210 85 86 #define PMUGRF_GPIO0A_SMT 0x0120 87 #define PMUGRF_SOC_CON0 0x0180 88 89 #define CCI_FORCE_WAKEUP WMSK_BIT(8) 90 #define EXTERNAL_32K WMSK_BIT(0) 91 92 #define PLL_PD_HW 0xff 93 #define IOMUX_CLK_32K 0x00030002 94 #define NOC_AUTO_ENABLE 0x3fffffff 95 96 #define SAVE_QOS(array, NAME) \ 97 RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 98 #define RESTORE_QOS(array, NAME) \ 99 RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 100 101 #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ 102 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ 103 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ 104 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ 105 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ 106 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ 107 array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ 108 array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ 109 } while (0) 110 111 #define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ 112 mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ 113 mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ 114 mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ 115 mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ 116 mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ 117 mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ 118 mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ 119 } while (0) 120 121 struct pmu_slpdata_s { 122 uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; 123 uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; 124 uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; 125 uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; 126 uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; 127 uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; 128 uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; 129 uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; 130 uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; 131 uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; 132 uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; 133 uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; 134 uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; 135 uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; 136 uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; 137 uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; 138 uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; 139 uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; 140 uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; 141 uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; 142 uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; 143 uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; 144 uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; 145 uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; 146 uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; 147 uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; 148 uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; 149 uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; 150 uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; 151 uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; 152 uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; 153 uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; 154 uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 155 uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 156 uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 157 uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; 158 }; 159 160 extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; 161 162 extern void sram_func_set_ddrctl_pll(uint32_t pll_src); 163 164 #endif /* __PMU_H__ */ 165