1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bakery_lock.h> 34 #include <debug.h> 35 #include <delay_timer.h> 36 #include <errno.h> 37 #include <gpio.h> 38 #include <mmio.h> 39 #include <platform.h> 40 #include <platform_def.h> 41 #include <plat_params.h> 42 #include <plat_private.h> 43 #include <rk3399_def.h> 44 #include <pmu_sram.h> 45 #include <soc.h> 46 #include <pmu.h> 47 #include <pmu_com.h> 48 #include <pwm.h> 49 #include <soc.h> 50 51 DEFINE_BAKERY_LOCK(rockchip_pd_lock); 52 53 static struct psram_data_t *psram_sleep_cfg = 54 (struct psram_data_t *)PSRAM_DT_BASE; 55 56 static uint32_t cpu_warm_boot_addr; 57 58 /* 59 * There are two ways to powering on or off on core. 60 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg, 61 * it is core_pwr_pd mode 62 * 2) Enable the core power manage in PMU_CORE_PM_CON reg, 63 * then, if the core enter into wfi, it power domain will be 64 * powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode 65 * so we need core_pm_cfg_info to distinguish which method be used now. 66 */ 67 68 static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT] 69 #if USE_COHERENT_MEM 70 __attribute__ ((section("tzfw_coherent_mem"))) 71 #endif 72 ;/* coheront */ 73 74 static void pmu_bus_idle_req(uint32_t bus, uint32_t state) 75 { 76 uint32_t bus_id = BIT(bus); 77 uint32_t bus_req; 78 uint32_t wait_cnt = 0; 79 uint32_t bus_state, bus_ack; 80 81 if (state) 82 bus_req = BIT(bus); 83 else 84 bus_req = 0; 85 86 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); 87 88 do { 89 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; 90 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; 91 wait_cnt++; 92 } while ((bus_state != bus_req || bus_ack != bus_req) && 93 (wait_cnt < MAX_WAIT_COUNT)); 94 95 if (bus_state != bus_req || bus_ack != bus_req) { 96 INFO("%s:st=%x(%x)\n", __func__, 97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), 98 bus_state); 99 INFO("%s:st=%x(%x)\n", __func__, 100 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), 101 bus_ack); 102 } 103 104 } 105 106 struct pmu_slpdata_s pmu_slpdata; 107 108 static void qos_save(void) 109 { 110 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) 111 RESTORE_QOS(pmu_slpdata.gpu_qos, GPU); 112 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { 113 RESTORE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); 114 RESTORE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); 115 } 116 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { 117 RESTORE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); 118 RESTORE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); 119 } 120 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { 121 RESTORE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); 122 RESTORE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); 123 RESTORE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); 124 } 125 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) 126 RESTORE_QOS(pmu_slpdata.hdcp_qos, HDCP); 127 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) 128 RESTORE_QOS(pmu_slpdata.gmac_qos, GMAC); 129 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { 130 RESTORE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); 131 RESTORE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); 132 } 133 if (pmu_power_domain_st(PD_SD) == pmu_pd_on) 134 RESTORE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); 135 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) 136 RESTORE_QOS(pmu_slpdata.emmc_qos, EMMC); 137 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) 138 RESTORE_QOS(pmu_slpdata.sdio_qos, SDIO); 139 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) 140 RESTORE_QOS(pmu_slpdata.gic_qos, GIC); 141 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { 142 RESTORE_QOS(pmu_slpdata.rga_r_qos, RGA_R); 143 RESTORE_QOS(pmu_slpdata.rga_w_qos, RGA_W); 144 } 145 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) 146 RESTORE_QOS(pmu_slpdata.iep_qos, IEP); 147 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { 148 RESTORE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); 149 RESTORE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); 150 } 151 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { 152 RESTORE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); 153 RESTORE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); 154 RESTORE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); 155 } 156 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { 157 RESTORE_QOS(pmu_slpdata.dmac0_qos, DMAC0); 158 RESTORE_QOS(pmu_slpdata.dmac1_qos, DMAC1); 159 RESTORE_QOS(pmu_slpdata.dcf_qos, DCF); 160 RESTORE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); 161 RESTORE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); 162 RESTORE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); 163 RESTORE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); 164 RESTORE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); 165 } 166 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) 167 RESTORE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); 168 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { 169 RESTORE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); 170 RESTORE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); 171 } 172 } 173 174 static void qos_restore(void) 175 { 176 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) 177 SAVE_QOS(pmu_slpdata.gpu_qos, GPU); 178 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { 179 SAVE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); 180 SAVE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); 181 } 182 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { 183 SAVE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); 184 SAVE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); 185 } 186 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { 187 SAVE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); 188 SAVE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); 189 SAVE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); 190 } 191 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) 192 SAVE_QOS(pmu_slpdata.hdcp_qos, HDCP); 193 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) 194 SAVE_QOS(pmu_slpdata.gmac_qos, GMAC); 195 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { 196 SAVE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); 197 SAVE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); 198 } 199 if (pmu_power_domain_st(PD_SD) == pmu_pd_on) 200 SAVE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); 201 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) 202 SAVE_QOS(pmu_slpdata.emmc_qos, EMMC); 203 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) 204 SAVE_QOS(pmu_slpdata.sdio_qos, SDIO); 205 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) 206 SAVE_QOS(pmu_slpdata.gic_qos, GIC); 207 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { 208 SAVE_QOS(pmu_slpdata.rga_r_qos, RGA_R); 209 SAVE_QOS(pmu_slpdata.rga_w_qos, RGA_W); 210 } 211 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) 212 SAVE_QOS(pmu_slpdata.iep_qos, IEP); 213 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { 214 SAVE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); 215 SAVE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); 216 } 217 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { 218 SAVE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); 219 SAVE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); 220 SAVE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); 221 } 222 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { 223 SAVE_QOS(pmu_slpdata.dmac0_qos, DMAC0); 224 SAVE_QOS(pmu_slpdata.dmac1_qos, DMAC1); 225 SAVE_QOS(pmu_slpdata.dcf_qos, DCF); 226 SAVE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); 227 SAVE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); 228 SAVE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); 229 SAVE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); 230 SAVE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); 231 } 232 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) 233 SAVE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); 234 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { 235 SAVE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); 236 SAVE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); 237 } 238 } 239 240 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 241 { 242 uint32_t state; 243 244 if (pmu_power_domain_st(pd_id) == pd_state) 245 goto out; 246 247 if (pd_state == pmu_pd_on) 248 pmu_power_domain_ctr(pd_id, pd_state); 249 250 state = (pd_state == pmu_pd_off) ? BUS_IDLE : BUS_ACTIVE; 251 252 switch (pd_id) { 253 case PD_GPU: 254 pmu_bus_idle_req(BUS_ID_GPU, state); 255 break; 256 case PD_VIO: 257 pmu_bus_idle_req(BUS_ID_VIO, state); 258 break; 259 case PD_ISP0: 260 pmu_bus_idle_req(BUS_ID_ISP0, state); 261 break; 262 case PD_ISP1: 263 pmu_bus_idle_req(BUS_ID_ISP1, state); 264 break; 265 case PD_VO: 266 pmu_bus_idle_req(BUS_ID_VOPB, state); 267 pmu_bus_idle_req(BUS_ID_VOPL, state); 268 break; 269 case PD_HDCP: 270 pmu_bus_idle_req(BUS_ID_HDCP, state); 271 break; 272 case PD_TCPD0: 273 break; 274 case PD_TCPD1: 275 break; 276 case PD_GMAC: 277 pmu_bus_idle_req(BUS_ID_GMAC, state); 278 break; 279 case PD_CCI: 280 pmu_bus_idle_req(BUS_ID_CCIM0, state); 281 pmu_bus_idle_req(BUS_ID_CCIM1, state); 282 break; 283 case PD_SD: 284 pmu_bus_idle_req(BUS_ID_SD, state); 285 break; 286 case PD_EMMC: 287 pmu_bus_idle_req(BUS_ID_EMMC, state); 288 break; 289 case PD_EDP: 290 pmu_bus_idle_req(BUS_ID_EDP, state); 291 break; 292 case PD_SDIOAUDIO: 293 pmu_bus_idle_req(BUS_ID_SDIOAUDIO, state); 294 break; 295 case PD_GIC: 296 pmu_bus_idle_req(BUS_ID_GIC, state); 297 break; 298 case PD_RGA: 299 pmu_bus_idle_req(BUS_ID_RGA, state); 300 break; 301 case PD_VCODEC: 302 pmu_bus_idle_req(BUS_ID_VCODEC, state); 303 break; 304 case PD_VDU: 305 pmu_bus_idle_req(BUS_ID_VDU, state); 306 break; 307 case PD_IEP: 308 pmu_bus_idle_req(BUS_ID_IEP, state); 309 break; 310 case PD_USB3: 311 pmu_bus_idle_req(BUS_ID_USB3, state); 312 break; 313 case PD_PERIHP: 314 pmu_bus_idle_req(BUS_ID_PERIHP, state); 315 break; 316 default: 317 break; 318 } 319 320 if (pd_state == pmu_pd_off) 321 pmu_power_domain_ctr(pd_id, pd_state); 322 323 out: 324 return 0; 325 } 326 327 static uint32_t pmu_powerdomain_state; 328 329 static void pmu_power_domains_suspend(void) 330 { 331 clk_gate_con_save(); 332 clk_gate_con_disable(); 333 qos_save(); 334 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 335 pmu_set_power_domain(PD_GPU, pmu_pd_off); 336 pmu_set_power_domain(PD_TCPD0, pmu_pd_off); 337 pmu_set_power_domain(PD_TCPD1, pmu_pd_off); 338 pmu_set_power_domain(PD_VO, pmu_pd_off); 339 pmu_set_power_domain(PD_ISP0, pmu_pd_off); 340 pmu_set_power_domain(PD_ISP1, pmu_pd_off); 341 pmu_set_power_domain(PD_HDCP, pmu_pd_off); 342 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_off); 343 pmu_set_power_domain(PD_GMAC, pmu_pd_off); 344 pmu_set_power_domain(PD_EDP, pmu_pd_off); 345 pmu_set_power_domain(PD_IEP, pmu_pd_off); 346 pmu_set_power_domain(PD_RGA, pmu_pd_off); 347 pmu_set_power_domain(PD_VCODEC, pmu_pd_off); 348 pmu_set_power_domain(PD_VDU, pmu_pd_off); 349 clk_gate_con_restore(); 350 } 351 352 static void pmu_power_domains_resume(void) 353 { 354 clk_gate_con_save(); 355 clk_gate_con_disable(); 356 if (!(pmu_powerdomain_state & BIT(PD_VDU))) 357 pmu_set_power_domain(PD_VDU, pmu_pd_on); 358 if (!(pmu_powerdomain_state & BIT(PD_VCODEC))) 359 pmu_set_power_domain(PD_VCODEC, pmu_pd_on); 360 if (!(pmu_powerdomain_state & BIT(PD_RGA))) 361 pmu_set_power_domain(PD_RGA, pmu_pd_on); 362 if (!(pmu_powerdomain_state & BIT(PD_IEP))) 363 pmu_set_power_domain(PD_IEP, pmu_pd_on); 364 if (!(pmu_powerdomain_state & BIT(PD_EDP))) 365 pmu_set_power_domain(PD_EDP, pmu_pd_on); 366 if (!(pmu_powerdomain_state & BIT(PD_GMAC))) 367 pmu_set_power_domain(PD_GMAC, pmu_pd_on); 368 if (!(pmu_powerdomain_state & BIT(PD_SDIOAUDIO))) 369 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); 370 if (!(pmu_powerdomain_state & BIT(PD_HDCP))) 371 pmu_set_power_domain(PD_HDCP, pmu_pd_on); 372 if (!(pmu_powerdomain_state & BIT(PD_ISP1))) 373 pmu_set_power_domain(PD_ISP1, pmu_pd_on); 374 if (!(pmu_powerdomain_state & BIT(PD_ISP0))) 375 pmu_set_power_domain(PD_ISP0, pmu_pd_on); 376 if (!(pmu_powerdomain_state & BIT(PD_VO))) 377 pmu_set_power_domain(PD_VO, pmu_pd_on); 378 if (!(pmu_powerdomain_state & BIT(PD_TCPD1))) 379 pmu_set_power_domain(PD_TCPD1, pmu_pd_on); 380 if (!(pmu_powerdomain_state & BIT(PD_TCPD0))) 381 pmu_set_power_domain(PD_TCPD0, pmu_pd_on); 382 if (!(pmu_powerdomain_state & BIT(PD_GPU))) 383 pmu_set_power_domain(PD_GPU, pmu_pd_on); 384 qos_restore(); 385 clk_gate_con_restore(); 386 } 387 388 void rk3399_flash_l2_b(void) 389 { 390 uint32_t wait_cnt = 0; 391 392 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); 393 dsb(); 394 395 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & 396 BIT(L2_FLUSHDONE_CLUSTER_B))) { 397 wait_cnt++; 398 if (wait_cnt >= MAX_WAIT_COUNT) 399 WARN("%s:reg %x,wait\n", __func__, 400 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); 401 } 402 403 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); 404 } 405 406 static void pmu_scu_b_pwrdn(void) 407 { 408 uint32_t wait_cnt = 0; 409 410 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & 411 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) != 412 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) { 413 ERROR("%s: not all cpus is off\n", __func__); 414 return; 415 } 416 417 rk3399_flash_l2_b(); 418 419 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); 420 421 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & 422 BIT(STANDBY_BY_WFIL2_CLUSTER_B))) { 423 wait_cnt++; 424 if (wait_cnt >= MAX_WAIT_COUNT) 425 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 426 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); 427 } 428 } 429 430 static void pmu_scu_b_pwrup(void) 431 { 432 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); 433 } 434 435 void plat_rockchip_pmusram_prepare(void) 436 { 437 uint32_t *sram_dst, *sram_src; 438 size_t sram_size = 2; 439 440 /* 441 * pmu sram code and data prepare 442 */ 443 sram_dst = (uint32_t *)PMUSRAM_BASE; 444 sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; 445 sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - 446 (uint32_t *)sram_src; 447 448 u32_align_cpy(sram_dst, sram_src, sram_size); 449 450 psram_sleep_cfg->sp = PSRAM_DT_BASE; 451 } 452 453 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) 454 { 455 assert(cpu_id < PLATFORM_CORE_COUNT); 456 return core_pm_cfg_info[cpu_id]; 457 } 458 459 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) 460 { 461 assert(cpu_id < PLATFORM_CORE_COUNT); 462 core_pm_cfg_info[cpu_id] = value; 463 #if !USE_COHERENT_MEM 464 flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id], 465 sizeof(uint32_t)); 466 #endif 467 } 468 469 static int cpus_power_domain_on(uint32_t cpu_id) 470 { 471 uint32_t cfg_info; 472 uint32_t cpu_pd = PD_CPUL0 + cpu_id; 473 /* 474 * There are two ways to powering on or off on core. 475 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg 476 * 2) Enable the core power manage in PMU_CORE_PM_CON reg, 477 * then, if the core enter into wfi, it power domain will be 478 * powered off automatically. 479 */ 480 481 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); 482 483 if (cfg_info == core_pwr_pd) { 484 /* disable core_pm cfg */ 485 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 486 CORES_PM_DISABLE); 487 /* if the cores have be on, power off it firstly */ 488 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { 489 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); 490 pmu_power_domain_ctr(cpu_pd, pmu_pd_off); 491 } 492 493 pmu_power_domain_ctr(cpu_pd, pmu_pd_on); 494 } else { 495 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { 496 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); 497 return -EINVAL; 498 } 499 500 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 501 BIT(core_pm_sft_wakeup_en)); 502 dsb(); 503 } 504 505 return 0; 506 } 507 508 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 509 { 510 uint32_t cpu_pd; 511 uint32_t core_pm_value; 512 513 cpu_pd = PD_CPUL0 + cpu_id; 514 if (pmu_power_domain_st(cpu_pd) == pmu_pd_off) 515 return 0; 516 517 if (pd_cfg == core_pwr_pd) { 518 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) 519 return -EINVAL; 520 521 /* disable core_pm cfg */ 522 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 523 CORES_PM_DISABLE); 524 525 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 526 pmu_power_domain_ctr(cpu_pd, pmu_pd_off); 527 } else { 528 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 529 530 core_pm_value = BIT(core_pm_en); 531 if (pd_cfg == core_pwr_wfi_int) 532 core_pm_value |= BIT(core_pm_int_wakeup_en); 533 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 534 core_pm_value); 535 dsb(); 536 } 537 538 return 0; 539 } 540 541 static inline void clst_pwr_domain_suspend(plat_local_state_t lvl_state) 542 { 543 uint32_t cpu_id = plat_my_core_pos(); 544 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; 545 546 assert(cpu_id < PLATFORM_CORE_COUNT); 547 548 if (lvl_state == PLAT_MAX_RET_STATE || 549 lvl_state == PLAT_MAX_OFF_STATE) { 550 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) { 551 pll_id = ALPLL_ID; 552 clst_st_msk = CLST_L_CPUS_MSK; 553 } else { 554 pll_id = ABPLL_ID; 555 clst_st_msk = CLST_B_CPUS_MSK << 556 PLATFORM_CLUSTER0_CORE_COUNT; 557 } 558 559 clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id)); 560 561 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 562 563 pmu_st &= clst_st_msk; 564 565 if (pmu_st == clst_st_chk_msk) { 566 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 567 PLL_SLOW_MODE); 568 569 clst_warmboot_data[pll_id] = PMU_CLST_RET; 570 571 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 572 pmu_st &= clst_st_msk; 573 if (pmu_st == clst_st_chk_msk) 574 return; 575 /* 576 * it is mean that others cpu is up again, 577 * we must resume the cfg at once. 578 */ 579 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 580 PLL_NOMAL_MODE); 581 clst_warmboot_data[pll_id] = 0; 582 } 583 } 584 } 585 586 static int clst_pwr_domain_resume(plat_local_state_t lvl_state) 587 { 588 uint32_t cpu_id = plat_my_core_pos(); 589 uint32_t pll_id, pll_st; 590 591 assert(cpu_id < PLATFORM_CORE_COUNT); 592 593 if (lvl_state == PLAT_MAX_RET_STATE || 594 lvl_state == PLAT_MAX_OFF_STATE) { 595 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) 596 pll_id = ALPLL_ID; 597 else 598 pll_id = ABPLL_ID; 599 600 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> 601 PLL_MODE_SHIFT; 602 603 if (pll_st != NORMAL_MODE) { 604 WARN("%s: clst (%d) is in error mode (%d)\n", 605 __func__, pll_id, pll_st); 606 return -1; 607 } 608 } 609 610 return 0; 611 } 612 613 static void nonboot_cpus_off(void) 614 { 615 uint32_t boot_cpu, cpu; 616 617 boot_cpu = plat_my_core_pos(); 618 619 /* turn off noboot cpus */ 620 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 621 if (cpu == boot_cpu) 622 continue; 623 cpus_power_domain_off(cpu, core_pwr_pd); 624 } 625 } 626 627 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) 628 { 629 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 630 631 assert(cpu_id < PLATFORM_CORE_COUNT); 632 assert(cpuson_flags[cpu_id] == 0); 633 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 634 cpuson_entry_point[cpu_id] = entrypoint; 635 dsb(); 636 637 cpus_power_domain_on(cpu_id); 638 639 return 0; 640 } 641 642 static int cores_pwr_domain_off(void) 643 { 644 uint32_t cpu_id = plat_my_core_pos(); 645 646 cpus_power_domain_off(cpu_id, core_pwr_wfi); 647 648 return 0; 649 } 650 651 static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state) 652 { 653 switch (lvl) { 654 case MPIDR_AFFLVL1: 655 clst_pwr_domain_suspend(lvl_state); 656 break; 657 default: 658 break; 659 } 660 661 return 0; 662 } 663 664 static int cores_pwr_domain_suspend(void) 665 { 666 uint32_t cpu_id = plat_my_core_pos(); 667 668 assert(cpu_id < PLATFORM_CORE_COUNT); 669 assert(cpuson_flags[cpu_id] == 0); 670 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 671 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 672 dsb(); 673 674 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 675 676 return 0; 677 } 678 679 static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state) 680 { 681 switch (lvl) { 682 case MPIDR_AFFLVL1: 683 clst_pwr_domain_suspend(lvl_state); 684 break; 685 default: 686 break; 687 } 688 689 return 0; 690 } 691 692 static int cores_pwr_domain_on_finish(void) 693 { 694 uint32_t cpu_id = plat_my_core_pos(); 695 696 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 697 CORES_PM_DISABLE); 698 return 0; 699 } 700 701 static int hlvl_pwr_domain_on_finish(uint32_t lvl, 702 plat_local_state_t lvl_state) 703 { 704 switch (lvl) { 705 case MPIDR_AFFLVL1: 706 clst_pwr_domain_resume(lvl_state); 707 break; 708 default: 709 break; 710 } 711 712 return 0; 713 } 714 715 static int cores_pwr_domain_resume(void) 716 { 717 uint32_t cpu_id = plat_my_core_pos(); 718 719 /* Disable core_pm */ 720 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); 721 722 return 0; 723 } 724 725 static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state) 726 { 727 switch (lvl) { 728 case MPIDR_AFFLVL1: 729 clst_pwr_domain_resume(lvl_state); 730 default: 731 break; 732 } 733 734 return 0; 735 } 736 737 static void sys_slp_config(void) 738 { 739 uint32_t slp_mode_cfg = 0; 740 741 mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP); 742 mmio_write_32(PMU_BASE + PMU_CCI500_CON, 743 BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | 744 BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | 745 BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); 746 747 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 748 BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | 749 BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | 750 BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); 751 752 slp_mode_cfg = BIT(PMU_PWR_MODE_EN) | 753 BIT(PMU_POWER_OFF_REQ_CFG) | 754 BIT(PMU_CPU0_PD_EN) | 755 BIT(PMU_L2_FLUSH_EN) | 756 BIT(PMU_L2_IDLE_EN) | 757 BIT(PMU_SCU_PD_EN) | 758 BIT(PMU_CCI_PD_EN) | 759 BIT(PMU_CLK_CORE_SRC_GATE_EN) | 760 BIT(PMU_PERILP_PD_EN) | 761 BIT(PMU_CLK_PERILP_SRC_GATE_EN) | 762 BIT(PMU_ALIVE_USE_LF) | 763 BIT(PMU_SREF0_ENTER_EN) | 764 BIT(PMU_SREF1_ENTER_EN) | 765 BIT(PMU_DDRC0_GATING_EN) | 766 BIT(PMU_DDRC1_GATING_EN) | 767 BIT(PMU_DDRIO0_RET_EN) | 768 BIT(PMU_DDRIO1_RET_EN) | 769 BIT(PMU_DDRIO_RET_HW_DE_REQ) | 770 BIT(PMU_PLL_PD_EN) | 771 BIT(PMU_CLK_CENTER_SRC_GATE_EN) | 772 BIT(PMU_OSC_DIS) | 773 BIT(PMU_PMU_USE_LF); 774 775 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_CLUSTER_L_WKUP_EN)); 776 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_CLUSTER_B_WKUP_EN)); 777 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); 778 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); 779 780 /* 781 * About to switch PMU counters to 32K; switch all timings to 32K 782 * for simplicity even if we don't plan on using them. 783 */ 784 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_32K_CNT_MS(3)); 785 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_32K_CNT_MS(3)); 786 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_32K_CNT_MS(3)); 787 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_32K_CNT_MS(3)); 788 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_32K_CNT_MS(3)); 789 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_32K_CNT_MS(3)); 790 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3)); 791 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(3)); 792 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_32K_CNT_MS(3)); 793 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_32K_CNT_MS(3)); 794 mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_32K_CNT_MS(3)); 795 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(3)); 796 797 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG)); 798 799 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); 800 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); 801 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ 802 } 803 804 static void sys_slp_unconfig(void) 805 { 806 /* 807 * About to switch PMU counters to 24M; switch all timings to 24M 808 * for simplicity even if we don't plan on using them. 809 */ 810 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(3)); 811 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(3)); 812 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(3)); 813 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_MS(3)); 814 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(3)); 815 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(3)); 816 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_24M_CNT_MS(3)); 817 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_24M_CNT_MS(3)); 818 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(3)); 819 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); 820 mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_MS(3)); 821 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(3)); 822 823 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG)); 824 } 825 826 static void set_hw_idle(uint32_t hw_idle) 827 { 828 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); 829 } 830 831 static void clr_hw_idle(uint32_t hw_idle) 832 { 833 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); 834 } 835 836 static int sys_pwr_domain_suspend(void) 837 { 838 uint32_t wait_cnt = 0; 839 uint32_t status = 0; 840 841 pmu_power_domains_suspend(); 842 set_hw_idle(BIT(PMU_CLR_CENTER1) | 843 BIT(PMU_CLR_ALIVE) | 844 BIT(PMU_CLR_MSCH0) | 845 BIT(PMU_CLR_MSCH1) | 846 BIT(PMU_CLR_CCIM0) | 847 BIT(PMU_CLR_CCIM1) | 848 BIT(PMU_CLR_CENTER) | 849 BIT(PMU_CLR_PERILP) | 850 BIT(PMU_CLR_PMU) | 851 BIT(PMU_CLR_PERILPM0) | 852 BIT(PMU_CLR_GIC)); 853 854 sys_slp_config(); 855 pmu_sgrf_rst_hld(); 856 857 mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), 858 (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | 859 CPU_BOOT_ADDR_WMASK); 860 861 pmu_scu_b_pwrdn(); 862 863 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 864 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | 865 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | 866 BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); 867 dsb(); 868 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | 869 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | 870 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); 871 while ((mmio_read_32(PMU_BASE + 872 PMU_ADB400_ST) & status) != status) { 873 wait_cnt++; 874 if (wait_cnt >= MAX_WAIT_COUNT) { 875 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 876 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); 877 panic(); 878 } 879 } 880 mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); 881 882 plls_suspend_prepare(); 883 disable_dvfs_plls(); 884 disable_pwms(); 885 disable_nodvfs_plls(); 886 887 return 0; 888 } 889 890 static int sys_pwr_domain_resume(void) 891 { 892 uint32_t wait_cnt = 0; 893 uint32_t status = 0; 894 895 enable_nodvfs_plls(); 896 enable_pwms(); 897 /* PWM regulators take time to come up; give 300us to be safe. */ 898 udelay(300); 899 enable_dvfs_plls(); 900 plls_resume_finish(); 901 902 sys_slp_unconfig(); 903 904 mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), 905 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | 906 CPU_BOOT_ADDR_WMASK); 907 908 mmio_write_32(PMU_BASE + PMU_CCI500_CON, 909 WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | 910 WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | 911 WMSK_BIT(PMU_QGATING_CCI500_CFG)); 912 dsb(); 913 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, 914 BIT(PMU_SCU_B_PWRDWN_EN)); 915 916 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 917 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | 918 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | 919 WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | 920 WMSK_BIT(PMU_CLR_CORE_L_HW) | 921 WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | 922 WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); 923 924 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | 925 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | 926 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); 927 928 while ((mmio_read_32(PMU_BASE + 929 PMU_ADB400_ST) & status)) { 930 wait_cnt++; 931 if (wait_cnt >= MAX_WAIT_COUNT) { 932 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 933 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); 934 panic(); 935 } 936 } 937 938 pmu_sgrf_rst_hld_release(); 939 pmu_scu_b_pwrup(); 940 941 pmu_power_domains_resume(); 942 clr_hw_idle(BIT(PMU_CLR_CENTER1) | 943 BIT(PMU_CLR_ALIVE) | 944 BIT(PMU_CLR_MSCH0) | 945 BIT(PMU_CLR_MSCH1) | 946 BIT(PMU_CLR_CCIM0) | 947 BIT(PMU_CLR_CCIM1) | 948 BIT(PMU_CLR_CENTER) | 949 BIT(PMU_CLR_PERILP) | 950 BIT(PMU_CLR_PMU) | 951 BIT(PMU_CLR_GIC)); 952 return 0; 953 } 954 955 void __dead2 soc_soft_reset(void) 956 { 957 struct gpio_info *rst_gpio; 958 959 rst_gpio = (struct gpio_info *)plat_get_rockchip_gpio_reset(); 960 961 if (rst_gpio) { 962 gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); 963 gpio_set_value(rst_gpio->index, rst_gpio->polarity); 964 } else { 965 soc_global_soft_reset(); 966 } 967 968 while (1) 969 ; 970 } 971 972 void __dead2 soc_system_off(void) 973 { 974 struct gpio_info *poweroff_gpio; 975 976 poweroff_gpio = (struct gpio_info *)plat_get_rockchip_gpio_poweroff(); 977 978 if (poweroff_gpio) { 979 /* 980 * if use tsadc over temp pin(GPIO1A6) as shutdown gpio, 981 * need to set this pin iomux back to gpio function 982 */ 983 if (poweroff_gpio->index == TSADC_INT_PIN) { 984 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, 985 GPIO1A6_IOMUX); 986 } 987 gpio_set_direction(poweroff_gpio->index, GPIO_DIR_OUT); 988 gpio_set_value(poweroff_gpio->index, poweroff_gpio->polarity); 989 } else { 990 WARN("Do nothing when system off\n"); 991 } 992 993 while (1) 994 ; 995 } 996 997 static struct rockchip_pm_ops_cb pm_ops = { 998 .cores_pwr_dm_on = cores_pwr_domain_on, 999 .cores_pwr_dm_off = cores_pwr_domain_off, 1000 .cores_pwr_dm_on_finish = cores_pwr_domain_on_finish, 1001 .cores_pwr_dm_suspend = cores_pwr_domain_suspend, 1002 .cores_pwr_dm_resume = cores_pwr_domain_resume, 1003 .hlvl_pwr_dm_suspend = hlvl_pwr_domain_suspend, 1004 .hlvl_pwr_dm_resume = hlvl_pwr_domain_resume, 1005 .hlvl_pwr_dm_off = hlvl_pwr_domain_off, 1006 .hlvl_pwr_dm_on_finish = hlvl_pwr_domain_on_finish, 1007 .sys_pwr_dm_suspend = sys_pwr_domain_suspend, 1008 .sys_pwr_dm_resume = sys_pwr_domain_resume, 1009 .sys_gbl_soft_reset = soc_soft_reset, 1010 .system_off = soc_system_off, 1011 }; 1012 1013 void plat_rockchip_pmu_init(void) 1014 { 1015 uint32_t cpu; 1016 1017 rockchip_pd_lock_init(); 1018 plat_setup_rockchip_pm_ops(&pm_ops); 1019 1020 /* register requires 32bits mode, switch it to 32 bits */ 1021 cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; 1022 1023 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1024 cpuson_flags[cpu] = 0; 1025 1026 for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++) 1027 clst_warmboot_data[cpu] = 0; 1028 1029 psram_sleep_cfg->ddr_func = 0x00; 1030 psram_sleep_cfg->ddr_data = 0x00; 1031 psram_sleep_cfg->ddr_flag = 0x00; 1032 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1033 1034 /* config cpu's warm boot address */ 1035 mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), 1036 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | 1037 CPU_BOOT_ADDR_WMASK); 1038 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); 1039 1040 nonboot_cpus_off(); 1041 1042 INFO("%s(%d): pd status %x\n", __func__, __LINE__, 1043 mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); 1044 } 1045