1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bakery_lock.h> 34 #include <debug.h> 35 #include <delay_timer.h> 36 #include <dfs.h> 37 #include <errno.h> 38 #include <gpio.h> 39 #include <mmio.h> 40 #include <m0_ctl.h> 41 #include <platform.h> 42 #include <platform_def.h> 43 #include <plat_params.h> 44 #include <plat_private.h> 45 #include <rk3399_def.h> 46 #include <pmu_sram.h> 47 #include <secure.h> 48 #include <soc.h> 49 #include <pmu.h> 50 #include <pmu_com.h> 51 #include <pwm.h> 52 #include <bl31.h> 53 #include <suspend.h> 54 55 DEFINE_BAKERY_LOCK(rockchip_pd_lock); 56 57 static struct psram_data_t *psram_sleep_cfg = 58 (struct psram_data_t *)PSRAM_DT_BASE; 59 60 static uint32_t cpu_warm_boot_addr; 61 62 /* 63 * There are two ways to powering on or off on core. 64 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg, 65 * it is core_pwr_pd mode 66 * 2) Enable the core power manage in PMU_CORE_PM_CON reg, 67 * then, if the core enter into wfi, it power domain will be 68 * powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode 69 * so we need core_pm_cfg_info to distinguish which method be used now. 70 */ 71 72 static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT] 73 #if USE_COHERENT_MEM 74 __attribute__ ((section("tzfw_coherent_mem"))) 75 #endif 76 ;/* coheront */ 77 78 static void pmu_bus_idle_req(uint32_t bus, uint32_t state) 79 { 80 uint32_t bus_id = BIT(bus); 81 uint32_t bus_req; 82 uint32_t wait_cnt = 0; 83 uint32_t bus_state, bus_ack; 84 85 if (state) 86 bus_req = BIT(bus); 87 else 88 bus_req = 0; 89 90 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); 91 92 do { 93 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; 94 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; 95 wait_cnt++; 96 } while ((bus_state != bus_req || bus_ack != bus_req) && 97 (wait_cnt < MAX_WAIT_COUNT)); 98 99 if (bus_state != bus_req || bus_ack != bus_req) { 100 INFO("%s:st=%x(%x)\n", __func__, 101 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), 102 bus_state); 103 INFO("%s:st=%x(%x)\n", __func__, 104 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), 105 bus_ack); 106 } 107 } 108 109 struct pmu_slpdata_s pmu_slpdata; 110 111 static void qos_save(void) 112 { 113 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) 114 RESTORE_QOS(pmu_slpdata.gpu_qos, GPU); 115 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { 116 RESTORE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); 117 RESTORE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); 118 } 119 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { 120 RESTORE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); 121 RESTORE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); 122 } 123 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { 124 RESTORE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); 125 RESTORE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); 126 RESTORE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); 127 } 128 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) 129 RESTORE_QOS(pmu_slpdata.hdcp_qos, HDCP); 130 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) 131 RESTORE_QOS(pmu_slpdata.gmac_qos, GMAC); 132 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { 133 RESTORE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); 134 RESTORE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); 135 } 136 if (pmu_power_domain_st(PD_SD) == pmu_pd_on) 137 RESTORE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); 138 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) 139 RESTORE_QOS(pmu_slpdata.emmc_qos, EMMC); 140 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) 141 RESTORE_QOS(pmu_slpdata.sdio_qos, SDIO); 142 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) 143 RESTORE_QOS(pmu_slpdata.gic_qos, GIC); 144 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { 145 RESTORE_QOS(pmu_slpdata.rga_r_qos, RGA_R); 146 RESTORE_QOS(pmu_slpdata.rga_w_qos, RGA_W); 147 } 148 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) 149 RESTORE_QOS(pmu_slpdata.iep_qos, IEP); 150 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { 151 RESTORE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); 152 RESTORE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); 153 } 154 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { 155 RESTORE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); 156 RESTORE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); 157 RESTORE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); 158 } 159 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { 160 RESTORE_QOS(pmu_slpdata.dmac0_qos, DMAC0); 161 RESTORE_QOS(pmu_slpdata.dmac1_qos, DMAC1); 162 RESTORE_QOS(pmu_slpdata.dcf_qos, DCF); 163 RESTORE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); 164 RESTORE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); 165 RESTORE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); 166 RESTORE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); 167 RESTORE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); 168 } 169 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) 170 RESTORE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); 171 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { 172 RESTORE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); 173 RESTORE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); 174 } 175 } 176 177 static void qos_restore(void) 178 { 179 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) 180 SAVE_QOS(pmu_slpdata.gpu_qos, GPU); 181 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { 182 SAVE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); 183 SAVE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); 184 } 185 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { 186 SAVE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); 187 SAVE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); 188 } 189 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { 190 SAVE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); 191 SAVE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); 192 SAVE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); 193 } 194 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) 195 SAVE_QOS(pmu_slpdata.hdcp_qos, HDCP); 196 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) 197 SAVE_QOS(pmu_slpdata.gmac_qos, GMAC); 198 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { 199 SAVE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); 200 SAVE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); 201 } 202 if (pmu_power_domain_st(PD_SD) == pmu_pd_on) 203 SAVE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); 204 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) 205 SAVE_QOS(pmu_slpdata.emmc_qos, EMMC); 206 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) 207 SAVE_QOS(pmu_slpdata.sdio_qos, SDIO); 208 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) 209 SAVE_QOS(pmu_slpdata.gic_qos, GIC); 210 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { 211 SAVE_QOS(pmu_slpdata.rga_r_qos, RGA_R); 212 SAVE_QOS(pmu_slpdata.rga_w_qos, RGA_W); 213 } 214 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) 215 SAVE_QOS(pmu_slpdata.iep_qos, IEP); 216 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { 217 SAVE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); 218 SAVE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); 219 } 220 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { 221 SAVE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); 222 SAVE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); 223 SAVE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); 224 } 225 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { 226 SAVE_QOS(pmu_slpdata.dmac0_qos, DMAC0); 227 SAVE_QOS(pmu_slpdata.dmac1_qos, DMAC1); 228 SAVE_QOS(pmu_slpdata.dcf_qos, DCF); 229 SAVE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); 230 SAVE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); 231 SAVE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); 232 SAVE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); 233 SAVE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); 234 } 235 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) 236 SAVE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); 237 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { 238 SAVE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); 239 SAVE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); 240 } 241 } 242 243 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 244 { 245 uint32_t state; 246 247 if (pmu_power_domain_st(pd_id) == pd_state) 248 goto out; 249 250 if (pd_state == pmu_pd_on) 251 pmu_power_domain_ctr(pd_id, pd_state); 252 253 state = (pd_state == pmu_pd_off) ? BUS_IDLE : BUS_ACTIVE; 254 255 switch (pd_id) { 256 case PD_GPU: 257 pmu_bus_idle_req(BUS_ID_GPU, state); 258 break; 259 case PD_VIO: 260 pmu_bus_idle_req(BUS_ID_VIO, state); 261 break; 262 case PD_ISP0: 263 pmu_bus_idle_req(BUS_ID_ISP0, state); 264 break; 265 case PD_ISP1: 266 pmu_bus_idle_req(BUS_ID_ISP1, state); 267 break; 268 case PD_VO: 269 pmu_bus_idle_req(BUS_ID_VOPB, state); 270 pmu_bus_idle_req(BUS_ID_VOPL, state); 271 break; 272 case PD_HDCP: 273 pmu_bus_idle_req(BUS_ID_HDCP, state); 274 break; 275 case PD_TCPD0: 276 break; 277 case PD_TCPD1: 278 break; 279 case PD_GMAC: 280 pmu_bus_idle_req(BUS_ID_GMAC, state); 281 break; 282 case PD_CCI: 283 pmu_bus_idle_req(BUS_ID_CCIM0, state); 284 pmu_bus_idle_req(BUS_ID_CCIM1, state); 285 break; 286 case PD_SD: 287 pmu_bus_idle_req(BUS_ID_SD, state); 288 break; 289 case PD_EMMC: 290 pmu_bus_idle_req(BUS_ID_EMMC, state); 291 break; 292 case PD_EDP: 293 pmu_bus_idle_req(BUS_ID_EDP, state); 294 break; 295 case PD_SDIOAUDIO: 296 pmu_bus_idle_req(BUS_ID_SDIOAUDIO, state); 297 break; 298 case PD_GIC: 299 pmu_bus_idle_req(BUS_ID_GIC, state); 300 break; 301 case PD_RGA: 302 pmu_bus_idle_req(BUS_ID_RGA, state); 303 break; 304 case PD_VCODEC: 305 pmu_bus_idle_req(BUS_ID_VCODEC, state); 306 break; 307 case PD_VDU: 308 pmu_bus_idle_req(BUS_ID_VDU, state); 309 break; 310 case PD_IEP: 311 pmu_bus_idle_req(BUS_ID_IEP, state); 312 break; 313 case PD_USB3: 314 pmu_bus_idle_req(BUS_ID_USB3, state); 315 break; 316 case PD_PERIHP: 317 pmu_bus_idle_req(BUS_ID_PERIHP, state); 318 break; 319 default: 320 break; 321 } 322 323 if (pd_state == pmu_pd_off) 324 pmu_power_domain_ctr(pd_id, pd_state); 325 326 out: 327 return 0; 328 } 329 330 static uint32_t pmu_powerdomain_state; 331 332 static void pmu_power_domains_suspend(void) 333 { 334 clk_gate_con_save(); 335 clk_gate_con_disable(); 336 qos_save(); 337 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 338 pmu_set_power_domain(PD_GPU, pmu_pd_off); 339 pmu_set_power_domain(PD_TCPD0, pmu_pd_off); 340 pmu_set_power_domain(PD_TCPD1, pmu_pd_off); 341 pmu_set_power_domain(PD_VO, pmu_pd_off); 342 pmu_set_power_domain(PD_ISP0, pmu_pd_off); 343 pmu_set_power_domain(PD_ISP1, pmu_pd_off); 344 pmu_set_power_domain(PD_HDCP, pmu_pd_off); 345 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_off); 346 pmu_set_power_domain(PD_GMAC, pmu_pd_off); 347 pmu_set_power_domain(PD_EDP, pmu_pd_off); 348 pmu_set_power_domain(PD_IEP, pmu_pd_off); 349 pmu_set_power_domain(PD_RGA, pmu_pd_off); 350 pmu_set_power_domain(PD_VCODEC, pmu_pd_off); 351 pmu_set_power_domain(PD_VDU, pmu_pd_off); 352 clk_gate_con_restore(); 353 } 354 355 static void pmu_power_domains_resume(void) 356 { 357 clk_gate_con_save(); 358 clk_gate_con_disable(); 359 if (!(pmu_powerdomain_state & BIT(PD_VDU))) 360 pmu_set_power_domain(PD_VDU, pmu_pd_on); 361 if (!(pmu_powerdomain_state & BIT(PD_VCODEC))) 362 pmu_set_power_domain(PD_VCODEC, pmu_pd_on); 363 if (!(pmu_powerdomain_state & BIT(PD_RGA))) 364 pmu_set_power_domain(PD_RGA, pmu_pd_on); 365 if (!(pmu_powerdomain_state & BIT(PD_IEP))) 366 pmu_set_power_domain(PD_IEP, pmu_pd_on); 367 if (!(pmu_powerdomain_state & BIT(PD_EDP))) 368 pmu_set_power_domain(PD_EDP, pmu_pd_on); 369 if (!(pmu_powerdomain_state & BIT(PD_GMAC))) 370 pmu_set_power_domain(PD_GMAC, pmu_pd_on); 371 if (!(pmu_powerdomain_state & BIT(PD_SDIOAUDIO))) 372 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); 373 if (!(pmu_powerdomain_state & BIT(PD_HDCP))) 374 pmu_set_power_domain(PD_HDCP, pmu_pd_on); 375 if (!(pmu_powerdomain_state & BIT(PD_ISP1))) 376 pmu_set_power_domain(PD_ISP1, pmu_pd_on); 377 if (!(pmu_powerdomain_state & BIT(PD_ISP0))) 378 pmu_set_power_domain(PD_ISP0, pmu_pd_on); 379 if (!(pmu_powerdomain_state & BIT(PD_VO))) 380 pmu_set_power_domain(PD_VO, pmu_pd_on); 381 if (!(pmu_powerdomain_state & BIT(PD_TCPD1))) 382 pmu_set_power_domain(PD_TCPD1, pmu_pd_on); 383 if (!(pmu_powerdomain_state & BIT(PD_TCPD0))) 384 pmu_set_power_domain(PD_TCPD0, pmu_pd_on); 385 if (!(pmu_powerdomain_state & BIT(PD_GPU))) 386 pmu_set_power_domain(PD_GPU, pmu_pd_on); 387 qos_restore(); 388 clk_gate_con_restore(); 389 } 390 391 void rk3399_flash_l2_b(void) 392 { 393 uint32_t wait_cnt = 0; 394 395 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); 396 dsb(); 397 398 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & 399 BIT(L2_FLUSHDONE_CLUSTER_B))) { 400 wait_cnt++; 401 if (wait_cnt >= MAX_WAIT_COUNT) 402 WARN("%s:reg %x,wait\n", __func__, 403 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); 404 } 405 406 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); 407 } 408 409 static void pmu_scu_b_pwrdn(void) 410 { 411 uint32_t wait_cnt = 0; 412 413 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & 414 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) != 415 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) { 416 ERROR("%s: not all cpus is off\n", __func__); 417 return; 418 } 419 420 rk3399_flash_l2_b(); 421 422 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); 423 424 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & 425 BIT(STANDBY_BY_WFIL2_CLUSTER_B))) { 426 wait_cnt++; 427 if (wait_cnt >= MAX_WAIT_COUNT) 428 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 429 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); 430 } 431 } 432 433 static void pmu_scu_b_pwrup(void) 434 { 435 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); 436 } 437 438 void plat_rockchip_pmusram_prepare(void) 439 { 440 uint32_t *sram_dst, *sram_src; 441 size_t sram_size; 442 443 /* 444 * pmu sram code and data prepare 445 */ 446 sram_dst = (uint32_t *)PMUSRAM_BASE; 447 sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; 448 sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - 449 (uint32_t *)sram_src; 450 451 u32_align_cpy(sram_dst, sram_src, sram_size); 452 453 psram_sleep_cfg->sp = PSRAM_DT_BASE; 454 } 455 456 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) 457 { 458 assert(cpu_id < PLATFORM_CORE_COUNT); 459 return core_pm_cfg_info[cpu_id]; 460 } 461 462 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) 463 { 464 assert(cpu_id < PLATFORM_CORE_COUNT); 465 core_pm_cfg_info[cpu_id] = value; 466 #if !USE_COHERENT_MEM 467 flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id], 468 sizeof(uint32_t)); 469 #endif 470 } 471 472 static int cpus_power_domain_on(uint32_t cpu_id) 473 { 474 uint32_t cfg_info; 475 uint32_t cpu_pd = PD_CPUL0 + cpu_id; 476 /* 477 * There are two ways to powering on or off on core. 478 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg 479 * 2) Enable the core power manage in PMU_CORE_PM_CON reg, 480 * then, if the core enter into wfi, it power domain will be 481 * powered off automatically. 482 */ 483 484 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); 485 486 if (cfg_info == core_pwr_pd) { 487 /* disable core_pm cfg */ 488 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 489 CORES_PM_DISABLE); 490 /* if the cores have be on, power off it firstly */ 491 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { 492 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); 493 pmu_power_domain_ctr(cpu_pd, pmu_pd_off); 494 } 495 496 pmu_power_domain_ctr(cpu_pd, pmu_pd_on); 497 } else { 498 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { 499 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); 500 return -EINVAL; 501 } 502 503 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 504 BIT(core_pm_sft_wakeup_en)); 505 dsb(); 506 } 507 508 return 0; 509 } 510 511 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 512 { 513 uint32_t cpu_pd; 514 uint32_t core_pm_value; 515 516 cpu_pd = PD_CPUL0 + cpu_id; 517 if (pmu_power_domain_st(cpu_pd) == pmu_pd_off) 518 return 0; 519 520 if (pd_cfg == core_pwr_pd) { 521 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) 522 return -EINVAL; 523 524 /* disable core_pm cfg */ 525 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 526 CORES_PM_DISABLE); 527 528 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 529 pmu_power_domain_ctr(cpu_pd, pmu_pd_off); 530 } else { 531 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 532 533 core_pm_value = BIT(core_pm_en); 534 if (pd_cfg == core_pwr_wfi_int) 535 core_pm_value |= BIT(core_pm_int_wakeup_en); 536 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 537 core_pm_value); 538 dsb(); 539 } 540 541 return 0; 542 } 543 544 static inline void clst_pwr_domain_suspend(plat_local_state_t lvl_state) 545 { 546 uint32_t cpu_id = plat_my_core_pos(); 547 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; 548 549 assert(cpu_id < PLATFORM_CORE_COUNT); 550 551 if (lvl_state == PLAT_MAX_OFF_STATE) { 552 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) { 553 pll_id = ALPLL_ID; 554 clst_st_msk = CLST_L_CPUS_MSK; 555 } else { 556 pll_id = ABPLL_ID; 557 clst_st_msk = CLST_B_CPUS_MSK << 558 PLATFORM_CLUSTER0_CORE_COUNT; 559 } 560 561 clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id)); 562 563 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 564 565 pmu_st &= clst_st_msk; 566 567 if (pmu_st == clst_st_chk_msk) { 568 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 569 PLL_SLOW_MODE); 570 571 clst_warmboot_data[pll_id] = PMU_CLST_RET; 572 573 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); 574 pmu_st &= clst_st_msk; 575 if (pmu_st == clst_st_chk_msk) 576 return; 577 /* 578 * it is mean that others cpu is up again, 579 * we must resume the cfg at once. 580 */ 581 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 582 PLL_NOMAL_MODE); 583 clst_warmboot_data[pll_id] = 0; 584 } 585 } 586 } 587 588 static int clst_pwr_domain_resume(plat_local_state_t lvl_state) 589 { 590 uint32_t cpu_id = plat_my_core_pos(); 591 uint32_t pll_id, pll_st; 592 593 assert(cpu_id < PLATFORM_CORE_COUNT); 594 595 if (lvl_state == PLAT_MAX_OFF_STATE) { 596 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) 597 pll_id = ALPLL_ID; 598 else 599 pll_id = ABPLL_ID; 600 601 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> 602 PLL_MODE_SHIFT; 603 604 if (pll_st != NORMAL_MODE) { 605 WARN("%s: clst (%d) is in error mode (%d)\n", 606 __func__, pll_id, pll_st); 607 return -1; 608 } 609 } 610 611 return 0; 612 } 613 614 static void nonboot_cpus_off(void) 615 { 616 uint32_t boot_cpu, cpu; 617 618 boot_cpu = plat_my_core_pos(); 619 620 /* turn off noboot cpus */ 621 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 622 if (cpu == boot_cpu) 623 continue; 624 cpus_power_domain_off(cpu, core_pwr_pd); 625 } 626 } 627 628 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) 629 { 630 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 631 632 assert(cpu_id < PLATFORM_CORE_COUNT); 633 assert(cpuson_flags[cpu_id] == 0); 634 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 635 cpuson_entry_point[cpu_id] = entrypoint; 636 dsb(); 637 638 cpus_power_domain_on(cpu_id); 639 640 return PSCI_E_SUCCESS; 641 } 642 643 int rockchip_soc_cores_pwr_dm_off(void) 644 { 645 uint32_t cpu_id = plat_my_core_pos(); 646 647 cpus_power_domain_off(cpu_id, core_pwr_wfi); 648 649 return PSCI_E_SUCCESS; 650 } 651 652 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 653 plat_local_state_t lvl_state) 654 { 655 switch (lvl) { 656 case MPIDR_AFFLVL1: 657 clst_pwr_domain_suspend(lvl_state); 658 break; 659 default: 660 break; 661 } 662 663 return PSCI_E_SUCCESS; 664 } 665 666 int rockchip_soc_cores_pwr_dm_suspend(void) 667 { 668 uint32_t cpu_id = plat_my_core_pos(); 669 670 assert(cpu_id < PLATFORM_CORE_COUNT); 671 assert(cpuson_flags[cpu_id] == 0); 672 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 673 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 674 dsb(); 675 676 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 677 678 return PSCI_E_SUCCESS; 679 } 680 681 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) 682 { 683 switch (lvl) { 684 case MPIDR_AFFLVL1: 685 clst_pwr_domain_suspend(lvl_state); 686 break; 687 default: 688 break; 689 } 690 691 return PSCI_E_SUCCESS; 692 } 693 694 int rockchip_soc_cores_pwr_dm_on_finish(void) 695 { 696 uint32_t cpu_id = plat_my_core_pos(); 697 698 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 699 CORES_PM_DISABLE); 700 return PSCI_E_SUCCESS; 701 } 702 703 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 704 plat_local_state_t lvl_state) 705 { 706 switch (lvl) { 707 case MPIDR_AFFLVL1: 708 clst_pwr_domain_resume(lvl_state); 709 break; 710 default: 711 break; 712 } 713 714 return PSCI_E_SUCCESS; 715 } 716 717 int rockchip_soc_cores_pwr_dm_resume(void) 718 { 719 uint32_t cpu_id = plat_my_core_pos(); 720 721 /* Disable core_pm */ 722 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); 723 724 return PSCI_E_SUCCESS; 725 } 726 727 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) 728 { 729 switch (lvl) { 730 case MPIDR_AFFLVL1: 731 clst_pwr_domain_resume(lvl_state); 732 default: 733 break; 734 } 735 736 return PSCI_E_SUCCESS; 737 } 738 739 /** 740 * init_pmu_counts - Init timing counts in the PMU register area 741 * 742 * At various points when we power up or down parts of the system we need 743 * a delay to wait for power / clocks to become stable. The PMU has counters 744 * to help software do the delay properly. Basically, it works like this: 745 * - Software sets up counter values 746 * - When software turns on something in the PMU, the counter kicks off 747 * - The hardware sets a bit automatically when the counter has finished and 748 * software knows that the initialization is done. 749 * 750 * It's software's job to setup these counters. The hardware power on default 751 * for these settings is conservative, setting everything to 0x5dc0 752 * (750 ms in 32 kHz counts or 1 ms in 24 MHz counts). 753 * 754 * Note that some of these counters are only really used at suspend/resume 755 * time (for instance, that's the only time we turn off/on the oscillator) and 756 * others are used during normal runtime (like turning on/off a CPU or GPU) but 757 * it doesn't hurt to init everything at boot. 758 * 759 * Also note that these counters can run off the 32 kHz clock or the 24 MHz 760 * clock. While the 24 MHz clock can give us more precision, it's not always 761 * available (like when we turn the oscillator off at sleep time). The 762 * pmu_use_lf (lf: low freq) is available in power mode. Current understanding 763 * is that counts work like this: 764 * IF (pmu_use_lf == 0) || (power_mode_en == 0) 765 * use the 24M OSC for counts 766 * ELSE 767 * use the 32K OSC for counts 768 * 769 * Notes: 770 * - There is a separate bit for the PMU called PMU_24M_EN_CFG. At the moment 771 * we always keep that 0. This apparently choose between using the PLL as 772 * the source for the PMU vs. the 24M clock. If we ever set it to 1 we 773 * should consider how it affects these counts (if at all). 774 * - The power_mode_en is documented to auto-clear automatically when we leave 775 * "power mode". That's why most clocks are on 24M. Only timings used when 776 * in "power mode" are 32k. 777 * - In some cases the kernel may override these counts. 778 * 779 * The PMU_STABLE_CNT / PMU_OSC_CNT / PMU_PLLLOCK_CNT are important CNTs 780 * in power mode, we need to ensure that they are available. 781 */ 782 static void init_pmu_counts(void) 783 { 784 /* COUNTS FOR INSIDE POWER MODE */ 785 786 /* 787 * From limited testing, need PMU stable >= 2ms, but go overkill 788 * and choose 30 ms to match testing on past SoCs. Also let 789 * OSC have 30 ms for stabilization. 790 */ 791 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30)); 792 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30)); 793 794 /* Unclear what these should be; try 3 ms */ 795 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3)); 796 797 /* Unclear what this should be, but set the default explicitly */ 798 mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0); 799 800 /* COUNTS FOR OUTSIDE POWER MODE */ 801 802 /* Put something sorta conservative here until we know better */ 803 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); 804 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1)); 805 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1)); 806 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1)); 807 808 /* 809 * Set CPU/GPU to 1 us. 810 * 811 * NOTE: Even though ATF doesn't configure the GPU we'll still setup 812 * counts here. After all ATF controls all these other bits and also 813 * chooses which clock these counters use. 814 */ 815 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_US(1)); 816 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1)); 817 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1)); 818 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1)); 819 mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1)); 820 mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1)); 821 } 822 823 static uint32_t clk_ddrc_save; 824 825 static void sys_slp_config(void) 826 { 827 uint32_t slp_mode_cfg = 0; 828 829 /* keep enabling clk_ddrc_bpll_src_en gate for DDRC */ 830 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); 831 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); 832 833 prepare_abpll_for_ddrctrl(); 834 sram_func_set_ddrctl_pll(ABPLL_ID); 835 836 mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP); 837 mmio_write_32(PMU_BASE + PMU_CCI500_CON, 838 BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | 839 BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | 840 BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); 841 842 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 843 BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | 844 BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | 845 BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); 846 847 slp_mode_cfg = BIT(PMU_PWR_MODE_EN) | 848 BIT(PMU_POWER_OFF_REQ_CFG) | 849 BIT(PMU_CPU0_PD_EN) | 850 BIT(PMU_L2_FLUSH_EN) | 851 BIT(PMU_L2_IDLE_EN) | 852 BIT(PMU_SCU_PD_EN) | 853 BIT(PMU_CCI_PD_EN) | 854 BIT(PMU_CLK_CORE_SRC_GATE_EN) | 855 BIT(PMU_ALIVE_USE_LF) | 856 BIT(PMU_SREF0_ENTER_EN) | 857 BIT(PMU_SREF1_ENTER_EN) | 858 BIT(PMU_DDRC0_GATING_EN) | 859 BIT(PMU_DDRC1_GATING_EN) | 860 BIT(PMU_DDRIO0_RET_EN) | 861 BIT(PMU_DDRIO1_RET_EN) | 862 BIT(PMU_DDRIO_RET_HW_DE_REQ) | 863 BIT(PMU_CENTER_PD_EN) | 864 BIT(PMU_PLL_PD_EN) | 865 BIT(PMU_CLK_CENTER_SRC_GATE_EN) | 866 BIT(PMU_OSC_DIS) | 867 BIT(PMU_PMU_USE_LF); 868 869 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); 870 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); 871 872 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); 873 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); 874 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ 875 } 876 877 static void set_hw_idle(uint32_t hw_idle) 878 { 879 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); 880 } 881 882 static void clr_hw_idle(uint32_t hw_idle) 883 { 884 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); 885 } 886 887 static uint32_t iomux_status[12]; 888 static uint32_t pull_mode_status[12]; 889 static uint32_t gpio_direction[3]; 890 static uint32_t gpio_2_4_clk_gate; 891 892 static void suspend_apio(void) 893 { 894 struct apio_info *suspend_apio; 895 int i; 896 897 suspend_apio = plat_get_rockchip_suspend_apio(); 898 899 if (!suspend_apio) 900 return; 901 902 /* save gpio2 ~ gpio4 iomux and pull mode */ 903 for (i = 0; i < 12; i++) { 904 iomux_status[i] = mmio_read_32(GRF_BASE + 905 GRF_GPIO2A_IOMUX + i * 4); 906 pull_mode_status[i] = mmio_read_32(GRF_BASE + 907 GRF_GPIO2A_P + i * 4); 908 } 909 910 /* store gpio2 ~ gpio4 clock gate state */ 911 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> 912 PCLK_GPIO2_GATE_SHIFT) & 0x07; 913 914 /* enable gpio2 ~ gpio4 clock gate */ 915 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), 916 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT)); 917 918 /* save gpio2 ~ gpio4 direction */ 919 gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04); 920 gpio_direction[1] = mmio_read_32(GPIO3_BASE + 0x04); 921 gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04); 922 923 /* apio1 charge gpio3a0 ~ gpio3c7 */ 924 if (suspend_apio->apio1) { 925 926 /* set gpio3a0 ~ gpio3c7 iomux to gpio */ 927 mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX, 928 REG_SOC_WMSK | GRF_IOMUX_GPIO); 929 mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX, 930 REG_SOC_WMSK | GRF_IOMUX_GPIO); 931 mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX, 932 REG_SOC_WMSK | GRF_IOMUX_GPIO); 933 934 /* set gpio3a0 ~ gpio3c7 pull mode to pull none */ 935 mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0); 936 mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0); 937 mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0); 938 939 /* set gpio3a0 ~ gpio3c7 to input */ 940 mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff); 941 } 942 943 /* apio2 charge gpio2a0 ~ gpio2b4 */ 944 if (suspend_apio->apio2) { 945 946 /* set gpio2a0 ~ gpio2b4 iomux to gpio */ 947 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX, 948 REG_SOC_WMSK | GRF_IOMUX_GPIO); 949 mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX, 950 REG_SOC_WMSK | GRF_IOMUX_GPIO); 951 952 /* set gpio2a0 ~ gpio2b4 pull mode to pull none */ 953 mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0); 954 mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0); 955 956 /* set gpio2a0 ~ gpio2b4 to input */ 957 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff); 958 } 959 960 /* apio3 charge gpio2c0 ~ gpio2d4*/ 961 if (suspend_apio->apio3) { 962 963 /* set gpio2a0 ~ gpio2b4 iomux to gpio */ 964 mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX, 965 REG_SOC_WMSK | GRF_IOMUX_GPIO); 966 mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX, 967 REG_SOC_WMSK | GRF_IOMUX_GPIO); 968 969 /* set gpio2c0 ~ gpio2d4 pull mode to pull none */ 970 mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0); 971 mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0); 972 973 /* set gpio2c0 ~ gpio2d4 to input */ 974 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000); 975 } 976 977 /* apio4 charge gpio4c0 ~ gpio4c7, gpio4d0 ~ gpio4d6 */ 978 if (suspend_apio->apio4) { 979 980 /* set gpio4c0 ~ gpio4d6 iomux to gpio */ 981 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, 982 REG_SOC_WMSK | GRF_IOMUX_GPIO); 983 mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX, 984 REG_SOC_WMSK | GRF_IOMUX_GPIO); 985 986 /* set gpio4c0 ~ gpio4d6 pull mode to pull none */ 987 mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0); 988 mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0); 989 990 /* set gpio4c0 ~ gpio4d6 to input */ 991 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); 992 } 993 994 /* apio5 charge gpio3d0 ~ gpio3d7, gpio4a0 ~ gpio4a7*/ 995 if (suspend_apio->apio5) { 996 /* set gpio3d0 ~ gpio4a7 iomux to gpio */ 997 mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX, 998 REG_SOC_WMSK | GRF_IOMUX_GPIO); 999 mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX, 1000 REG_SOC_WMSK | GRF_IOMUX_GPIO); 1001 1002 /* set gpio3d0 ~ gpio4a7 pull mode to pull none */ 1003 mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0); 1004 mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0); 1005 1006 /* set gpio4c0 ~ gpio4d6 to input */ 1007 mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000); 1008 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); 1009 } 1010 } 1011 1012 static void resume_apio(void) 1013 { 1014 struct apio_info *suspend_apio; 1015 int i; 1016 1017 suspend_apio = plat_get_rockchip_suspend_apio(); 1018 1019 if (!suspend_apio) 1020 return; 1021 1022 for (i = 0; i < 12; i++) { 1023 mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4, 1024 REG_SOC_WMSK | pull_mode_status[i]); 1025 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4, 1026 REG_SOC_WMSK | iomux_status[i]); 1027 } 1028 1029 /* set gpio2 ~ gpio4 direction back to store value */ 1030 mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]); 1031 mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]); 1032 mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]); 1033 1034 /* set gpio2 ~ gpio4 clock gate back to store value */ 1035 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), 1036 BITS_WITH_WMASK(gpio_2_4_clk_gate, 0x07, 1037 PCLK_GPIO2_GATE_SHIFT)); 1038 } 1039 1040 static void suspend_gpio(void) 1041 { 1042 struct gpio_info *suspend_gpio; 1043 uint32_t count; 1044 int i; 1045 1046 suspend_gpio = plat_get_rockchip_suspend_gpio(&count); 1047 1048 for (i = 0; i < count; i++) { 1049 gpio_set_value(suspend_gpio[i].index, suspend_gpio[i].polarity); 1050 gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); 1051 udelay(1); 1052 } 1053 } 1054 1055 static void resume_gpio(void) 1056 { 1057 struct gpio_info *suspend_gpio; 1058 uint32_t count; 1059 int i; 1060 1061 suspend_gpio = plat_get_rockchip_suspend_gpio(&count); 1062 1063 for (i = count - 1; i >= 0; i--) { 1064 gpio_set_value(suspend_gpio[i].index, 1065 !suspend_gpio[i].polarity); 1066 gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); 1067 udelay(1); 1068 } 1069 } 1070 1071 static void m0_configure_suspend(void) 1072 { 1073 /* set PARAM to M0_FUNC_SUSPEND */ 1074 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND); 1075 } 1076 1077 int rockchip_soc_sys_pwr_dm_suspend(void) 1078 { 1079 uint32_t wait_cnt = 0; 1080 uint32_t status = 0; 1081 1082 ddr_prepare_for_sys_suspend(); 1083 dmc_save(); 1084 pmu_scu_b_pwrdn(); 1085 1086 pmu_power_domains_suspend(); 1087 set_hw_idle(BIT(PMU_CLR_CENTER1) | 1088 BIT(PMU_CLR_ALIVE) | 1089 BIT(PMU_CLR_MSCH0) | 1090 BIT(PMU_CLR_MSCH1) | 1091 BIT(PMU_CLR_CCIM0) | 1092 BIT(PMU_CLR_CCIM1) | 1093 BIT(PMU_CLR_CENTER) | 1094 BIT(PMU_CLR_GIC)); 1095 1096 sys_slp_config(); 1097 1098 m0_configure_suspend(); 1099 m0_start(); 1100 1101 pmu_sgrf_rst_hld(); 1102 1103 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), 1104 (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | 1105 CPU_BOOT_ADDR_WMASK); 1106 1107 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 1108 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | 1109 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | 1110 BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); 1111 dsb(); 1112 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | 1113 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | 1114 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); 1115 while ((mmio_read_32(PMU_BASE + 1116 PMU_ADB400_ST) & status) != status) { 1117 wait_cnt++; 1118 if (wait_cnt >= MAX_WAIT_COUNT) { 1119 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 1120 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); 1121 panic(); 1122 } 1123 } 1124 mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); 1125 1126 secure_watchdog_disable(); 1127 1128 /* 1129 * Disabling PLLs/PWM/DVFS is approaching WFI which is 1130 * the last steps in suspend. 1131 */ 1132 disable_dvfs_plls(); 1133 disable_pwms(); 1134 disable_nodvfs_plls(); 1135 1136 suspend_apio(); 1137 suspend_gpio(); 1138 1139 return 0; 1140 } 1141 1142 int rockchip_soc_sys_pwr_dm_resume(void) 1143 { 1144 uint32_t wait_cnt = 0; 1145 uint32_t status = 0; 1146 1147 resume_apio(); 1148 resume_gpio(); 1149 enable_nodvfs_plls(); 1150 enable_pwms(); 1151 /* PWM regulators take time to come up; give 300us to be safe. */ 1152 udelay(300); 1153 enable_dvfs_plls(); 1154 1155 secure_watchdog_enable(); 1156 1157 /* restore clk_ddrc_bpll_src_en gate */ 1158 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), 1159 BITS_WITH_WMASK(clk_ddrc_save, 0xff, 0)); 1160 1161 /* 1162 * The wakeup status is not cleared by itself, we need to clear it 1163 * manually. Otherwise we will alway query some interrupt next time. 1164 * 1165 * NOTE: If the kernel needs to query this, we might want to stash it 1166 * somewhere. 1167 */ 1168 mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); 1169 mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); 1170 1171 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), 1172 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | 1173 CPU_BOOT_ADDR_WMASK); 1174 1175 mmio_write_32(PMU_BASE + PMU_CCI500_CON, 1176 WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | 1177 WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | 1178 WMSK_BIT(PMU_QGATING_CCI500_CFG)); 1179 dsb(); 1180 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, 1181 BIT(PMU_SCU_B_PWRDWN_EN)); 1182 1183 mmio_write_32(PMU_BASE + PMU_ADB400_CON, 1184 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | 1185 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | 1186 WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | 1187 WMSK_BIT(PMU_CLR_CORE_L_HW) | 1188 WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | 1189 WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); 1190 1191 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | 1192 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | 1193 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); 1194 1195 while ((mmio_read_32(PMU_BASE + 1196 PMU_ADB400_ST) & status)) { 1197 wait_cnt++; 1198 if (wait_cnt >= MAX_WAIT_COUNT) { 1199 ERROR("%s:wait cluster-b l2(%x)\n", __func__, 1200 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); 1201 panic(); 1202 } 1203 } 1204 1205 pmu_sgrf_rst_hld_release(); 1206 pmu_scu_b_pwrup(); 1207 pmu_power_domains_resume(); 1208 1209 restore_dpll(); 1210 sram_func_set_ddrctl_pll(DPLL_ID); 1211 restore_abpll(); 1212 1213 clr_hw_idle(BIT(PMU_CLR_CENTER1) | 1214 BIT(PMU_CLR_ALIVE) | 1215 BIT(PMU_CLR_MSCH0) | 1216 BIT(PMU_CLR_MSCH1) | 1217 BIT(PMU_CLR_CCIM0) | 1218 BIT(PMU_CLR_CCIM1) | 1219 BIT(PMU_CLR_CENTER) | 1220 BIT(PMU_CLR_GIC)); 1221 1222 plat_rockchip_gic_cpuif_enable(); 1223 m0_stop(); 1224 1225 ddr_prepare_for_sys_resume(); 1226 1227 return 0; 1228 } 1229 1230 void __dead2 rockchip_soc_soft_reset(void) 1231 { 1232 struct gpio_info *rst_gpio; 1233 1234 rst_gpio = plat_get_rockchip_gpio_reset(); 1235 1236 if (rst_gpio) { 1237 gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); 1238 gpio_set_value(rst_gpio->index, rst_gpio->polarity); 1239 } else { 1240 soc_global_soft_reset(); 1241 } 1242 1243 while (1) 1244 ; 1245 } 1246 1247 void __dead2 rockchip_soc_system_off(void) 1248 { 1249 struct gpio_info *poweroff_gpio; 1250 1251 poweroff_gpio = plat_get_rockchip_gpio_poweroff(); 1252 1253 if (poweroff_gpio) { 1254 /* 1255 * if use tsadc over temp pin(GPIO1A6) as shutdown gpio, 1256 * need to set this pin iomux back to gpio function 1257 */ 1258 if (poweroff_gpio->index == TSADC_INT_PIN) { 1259 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, 1260 GPIO1A6_IOMUX); 1261 } 1262 gpio_set_direction(poweroff_gpio->index, GPIO_DIR_OUT); 1263 gpio_set_value(poweroff_gpio->index, poweroff_gpio->polarity); 1264 } else { 1265 WARN("Do nothing when system off\n"); 1266 } 1267 1268 while (1) 1269 ; 1270 } 1271 1272 void plat_rockchip_pmu_init(void) 1273 { 1274 uint32_t cpu; 1275 1276 rockchip_pd_lock_init(); 1277 1278 /* register requires 32bits mode, switch it to 32 bits */ 1279 cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; 1280 1281 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1282 cpuson_flags[cpu] = 0; 1283 1284 for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++) 1285 clst_warmboot_data[cpu] = 0; 1286 1287 psram_sleep_cfg->ddr_func = (uint64_t)dmc_restore; 1288 psram_sleep_cfg->ddr_data = (uint64_t)&sdram_config; 1289 psram_sleep_cfg->ddr_flag = 0x01; 1290 1291 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1292 1293 /* config cpu's warm boot address */ 1294 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), 1295 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | 1296 CPU_BOOT_ADDR_WMASK); 1297 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); 1298 1299 /* 1300 * Enable Schmitt trigger for better 32 kHz input signal, which is 1301 * important for suspend/resume reliability among other things. 1302 */ 1303 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); 1304 1305 init_pmu_counts(); 1306 1307 nonboot_cpus_off(); 1308 1309 INFO("%s(%d): pd status %x\n", __func__, __LINE__, 1310 mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); 1311 } 1312