1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <arch.h> 28#include <asm_macros.S> 29#include <platform_def.h> 30#include <pmu_regs.h> 31 32 .globl clst_warmboot_data 33 34 .macro sram_func _name 35 .section .sram.text, "ax" 36 .type \_name, %function 37 .func \_name 38 \_name: 39 .endm 40 41#define CRU_CLKSEL_CON6 0x118 42 43#define DDRCTL0_C_SYSREQ_CFG 0x0100 44#define DDRCTL1_C_SYSREQ_CFG 0x1000 45 46#define DDRC0_SREF_DONE_EXT 0x01 47#define DDRC1_SREF_DONE_EXT 0x04 48 49#define PLL_MODE_SHIFT (0x8) 50#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \ 51 (0x1 << PLL_MODE_SHIFT)) 52#define MPIDR_CLST_L_BITS 0x0 53 /* 54 * For different socs, if we want to speed up warmboot, 55 * we need to config some regs here. 56 * If scu was suspend, we must resume related clk 57 * from slow (24M) mode to normal mode first. 58 * X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK 59 */ 60.macro func_rockchip_clst_warmboot 61 adr x4, clst_warmboot_data 62 lsr x5, x0, #6 63 ldr w3, [x4, x5] 64 str wzr, [x4, x5] 65 cmp w3, #PMU_CLST_RET 66 b.ne clst_warmboot_end 67 ldr w6, =(PLL_NORMAL_MODE) 68 /* 69 * core_l offset is CRU_BASE + 0xc, 70 * core_b offset is CRU_BASE + 0x2c 71 */ 72 ldr x7, =(CRU_BASE + 0xc) 73 lsr x2, x0, #3 74 str w6, [x7, x2] 75clst_warmboot_end: 76.endm 77 78.macro rockchip_clst_warmboot_data 79clst_warmboot_data: 80 .rept PLATFORM_CLUSTER_COUNT 81 .word 0 82 .endr 83.endm 84 85 /* ----------------------------------------------- 86 * void sram_func_set_ddrctl_pll(uint32_t pll_src) 87 * Function to switch the PLL source for ddrctrl 88 * In: x0 - The PLL of the clk_ddrc clock source 89 * out: None 90 * Clobber list : x0 - x3, x5, x8 - x10 91 * ----------------------------------------------- 92 */ 93 94 .globl sram_func_set_ddrctl_pll 95 96sram_func sram_func_set_ddrctl_pll 97 /* backup parameter */ 98 mov x8, x0 99 100 /* disable the MMU at EL3 */ 101 mrs x9, sctlr_el3 102 bic x10, x9, #(SCTLR_M_BIT) 103 msr sctlr_el3, x10 104 isb 105 dsb sy 106 107 /* enable ddrctl0_1 idle request */ 108 mov x5, PMU_BASE 109 ldr w0, [x5, #PMU_SFT_CON] 110 orr w0, w0, #DDRCTL0_C_SYSREQ_CFG 111 orr w0, w0, #DDRCTL1_C_SYSREQ_CFG 112 str w0, [x5, #PMU_SFT_CON] 113 114check_ddrc0_1_sref_enter: 115 ldr w1, [x5, #PMU_DDR_SREF_ST] 116 and w2, w1, #DDRC0_SREF_DONE_EXT 117 and w3, w1, #DDRC1_SREF_DONE_EXT 118 orr w2, w2, w3 119 cmp w2, #(DDRC0_SREF_DONE_EXT | DDRC1_SREF_DONE_EXT) 120 b.eq check_ddrc0_1_sref_enter 121 122 /* 123 * select a PLL for ddrctrl: 124 * x0 = 0: ALPLL 125 * x0 = 1: ABPLL 126 * x0 = 2: DPLL 127 * x0 = 3: GPLLL 128 */ 129 mov x5, CRU_BASE 130 lsl w0, w8, #4 131 orr w0, w0, #0x00300000 132 str w0, [x5, #CRU_CLKSEL_CON6] 133 134 /* disable ddrctl0_1 idle request */ 135 mov x5, PMU_BASE 136 ldr w0, [x5, #PMU_SFT_CON] 137 bic w0, w0, #DDRCTL0_C_SYSREQ_CFG 138 bic w0, w0, #DDRCTL1_C_SYSREQ_CFG 139 str w0, [x5, #PMU_SFT_CON] 140 141check_ddrc0_1_sref_exit: 142 ldr w1, [x5, #PMU_DDR_SREF_ST] 143 and w2, w1, #DDRC0_SREF_DONE_EXT 144 and w3, w1, #DDRC1_SREF_DONE_EXT 145 orr w2, w2, w3 146 cmp w2, #0x0 147 b.eq check_ddrc0_1_sref_exit 148 149 /* reenable the MMU at EL3 */ 150 msr sctlr_el3, x9 151 isb 152 dsb sy 153 154 ret 155endfunc sram_func_set_ddrctl_pll 156