1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <mmio.h> 36 #include <m0_ctl.h> 37 #include <plat_private.h> 38 #include <rk3399_def.h> 39 #include <soc.h> 40 41 void m0_init(void) 42 { 43 /* secure config for M0 */ 44 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 45 mmio_write_32(SGRF_BASE + SGRF_SOC_CON6, WMSK_BIT(12)); 46 47 /* set the execute address for M0 */ 48 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 49 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, 50 0xffff, 0)); 51 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 52 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 53 0xf, 0)); 54 55 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 56 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); 57 58 /* 59 * To switch the parent to xin24M and div == 1, 60 * 61 * We need to close most of the PLLs and clocks except the OSC 24MHz 62 * durning suspend, and this should be enough to supplies the ddrfreq, 63 * For the simple handle, we just keep the fixed 24MHz to supply the 64 * suspend and ddrfreq directly. 65 */ 66 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, 67 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); 68 69 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); 70 } 71 72 void m0_start(void) 73 { 74 /* enable clocks for M0 */ 75 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 76 BITS_WITH_WMASK(0x0, 0xf, 0)); 77 78 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ 79 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); 80 dmbst(); 81 82 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 83 BITS_WITH_WMASK(0x0, 0x4, 0)); 84 85 udelay(5); 86 /* start M0 */ 87 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 88 BITS_WITH_WMASK(0x0, 0x20, 0)); 89 dmbst(); 90 } 91 92 void m0_stop(void) 93 { 94 /* stop M0 */ 95 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 96 BITS_WITH_WMASK(0x24, 0x24, 0)); 97 98 /* disable clocks for M0 */ 99 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 100 BITS_WITH_WMASK(0xf, 0xf, 0)); 101 } 102 103 void m0_wait_done(void) 104 { 105 do { 106 /* 107 * Don't starve the M0 for access to SRAM, so delay before 108 * reading the PARAM_M0_DONE value again. 109 */ 110 udelay(5); 111 dsb(); 112 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG); 113 114 /* 115 * Let the M0 settle into WFI before we leave. This is so we don't reset 116 * the M0 in a bad spot which can cause problems with the M0. 117 */ 118 udelay(10); 119 dsb(); 120 } 121