1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 14 #include <m0_ctl.h> 15 #include <plat_private.h> 16 #include <rk3399_def.h> 17 #include <secure.h> 18 #include <soc.h> 19 20 void m0_init(void) 21 { 22 /* secure config for M0 */ 23 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 24 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); 25 26 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 27 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); 28 29 /* 30 * To switch the parent to xin24M and div == 1, 31 * 32 * We need to close most of the PLLs and clocks except the OSC 24MHz 33 * durning suspend, and this should be enough to supplies the ddrfreq, 34 * For the simple handle, we just keep the fixed 24MHz to supply the 35 * suspend and ddrfreq directly. 36 */ 37 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, 38 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); 39 40 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); 41 } 42 43 void m0_configure_execute_addr(uintptr_t addr) 44 { 45 /* set the execute address for M0 */ 46 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 47 BITS_WITH_WMASK((addr >> 12) & 0xffff, 48 0xffffu, 0)); 49 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 50 BITS_WITH_WMASK((addr >> 28) & 0xf, 51 0xfu, 0)); 52 } 53 54 void m0_start(void) 55 { 56 /* enable clocks for M0 */ 57 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 58 BITS_WITH_WMASK(0x0, 0xf, 0)); 59 60 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ 61 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); 62 dmbst(); 63 64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 65 BITS_WITH_WMASK(0x0, 0x4, 0)); 66 67 udelay(5); 68 /* start M0 */ 69 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 70 BITS_WITH_WMASK(0x0, 0x20, 0)); 71 dmbst(); 72 } 73 74 void m0_stop(void) 75 { 76 /* stop M0 */ 77 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 78 BITS_WITH_WMASK(0x24, 0x24, 0)); 79 80 /* disable clocks for M0 */ 81 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 82 BITS_WITH_WMASK(0xf, 0xf, 0)); 83 } 84 85 void m0_wait_done(void) 86 { 87 do { 88 /* 89 * Don't starve the M0 for access to SRAM, so delay before 90 * reading the PARAM_M0_DONE value again. 91 */ 92 udelay(5); 93 dsb(); 94 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG); 95 96 /* 97 * Let the M0 settle into WFI before we leave. This is so we don't reset 98 * the M0 in a bad spot which can cause problems with the M0. 99 */ 100 udelay(10); 101 dsb(); 102 } 103