xref: /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/suspend.c (revision 82cb2c1ad9897473743f08437d0a3995bed561b9)
1977001aaSXing Zheng /*
2977001aaSXing Zheng  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3977001aaSXing Zheng  *
4*82cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5977001aaSXing Zheng  */
6977001aaSXing Zheng 
71830f790SXing Zheng #include <pmu_regs.h>
8977001aaSXing Zheng #include "rk3399_mcu.h"
9977001aaSXing Zheng 
10977001aaSXing Zheng #define M0_SCR			0xe000ed10  /* System Control Register (SCR) */
11977001aaSXing Zheng 
12977001aaSXing Zheng #define SCR_SLEEPDEEP_SHIFT	(1 << 2)
13977001aaSXing Zheng 
14977001aaSXing Zheng void handle_suspend(void)
15977001aaSXing Zheng {
16977001aaSXing Zheng 	unsigned int status_value;
17977001aaSXing Zheng 
18977001aaSXing Zheng 	while (1) {
19977001aaSXing Zheng 		status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST);
20977001aaSXing Zheng 		if (status_value) {
21977001aaSXing Zheng 			mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01);
22977001aaSXing Zheng 			return;
23977001aaSXing Zheng 		}
24977001aaSXing Zheng 	}
25977001aaSXing Zheng 
26977001aaSXing Zheng 	/* m0 enter deep sleep mode */
27977001aaSXing Zheng 	mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT);
28977001aaSXing Zheng }
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